IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2013-06-13 14:55
VLSI Design of Transform and Quantization Units in Scalable Distributed Video Coding
Narumi Tanaka, Masashi Okada (Osaka Univ), Kazuhito Sakomizu (Osaka Univ/OKI), Takao Onoye (Osaka Univ) SIS2013-8
Abstract (in Japanese) (See Japanese page) 
(in English) In this research, we aim to realize an embedded system for distributed video coding (DVC) encoder. Since transform and quantization processes of DVC encoding are the most dominant, we discuss architecture for its hardware implementation. In the proposed architecture, the transform and quantization processes are implemented in parallel by processing multiple pixels simultaneously, and the resource utilization is reduced by replacing equations used in DVC encoding with equivalent ones, which are suitable for hardware implementation. We implemented our architecture with Verilog HDL and evaluated it. In the experimental result, our hardware implementation achieved 30 fps encoding performance for $1920times1080$ resolution videos.
Keyword (in Japanese) (See Japanese page) 
(in English) Distributed Video Coding / transform / quantization / VLSI architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 78, SIS2013-8, pp. 39-44, June 2013.
Paper # SIS2013-8 
Date of Issue 2013-06-06 (SIS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2013-8

Conference Information
Committee SIS  
Conference Date 2013-06-13 - 2013-06-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Houzan Hall (Kagoshima) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2013-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) VLSI Design of Transform and Quantization Units in Scalable Distributed Video Coding 
Sub Title (in English)  
Keyword(1) Distributed Video Coding  
Keyword(2) transform  
Keyword(3) quantization  
Keyword(4) VLSI architecture  
1st Author's Name Narumi Tanaka  
1st Author's Affiliation Osaka University (Osaka Univ)
2nd Author's Name Masashi Okada  
2nd Author's Affiliation Osaka University (Osaka Univ)
3rd Author's Name Kazuhito Sakomizu  
3rd Author's Affiliation Osaka University/Oki Electric Industry Co., Ltd. (Osaka Univ/OKI)
4th Author's Name Takao Onoye  
4th Author's Affiliation Osaka University (Osaka Univ)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2013-06-13 14:55:00 
Presentation Time 20 
Registration for SIS 
Paper # SIS2013-8 
Volume (vol) 113 
Number (no) no.78 
Page pp.39-44 
Date of Issue 2013-06-06 (SIS) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan