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Paper Abstract and Keywords
Presentation 2013-07-04 16:25
[Invited Talk] Fabrication of Stacked Logic Circuits for Printed Integrated Circuits
Kazuhiro Kudo, Isao Kodera, Hiroshi Yamauchi, Shigekazu Kuniyoshi, Masatoshi Sakai (Chiba Univ.) OME2013-47
Abstract (in Japanese) (See Japanese page) 
(in English) We have demonstrated logic circuit operations of stacked-structure thin film transistor (TFT) circuits using TIPS-pentacene (6,13-Bis(triisopropylsilylethynyl)pentacene) and soluble ZnO as active layers. Bottom-gate-type TIPS-pentacene TFTs, as p-channel transistors, were formed on top-gate-type ZnO TFTs with common gate electrodes. For both TFTs, solution-processed silicone-resin layers were used as gate dielectric. The stacked-structure TFT circuit has several advantages such as easiness of active material patterning, compact device area per stage, and the short length of the interconnection as compared with the planar configuration in a conventional logic circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) Stacked Structure TFT / Logic Circuit / Silicone-resin / TIPS-pentacene / ZnO / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 115, OME2013-47, pp. 25-30, July 2013.
Paper # OME2013-47 
Date of Issue 2013-06-27 (OME) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF OME2013-47

Conference Information
Committee OME IEE-DEI  
Conference Date 2013-07-04 - 2013-07-05 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To OME 
Conference Code 2013-07-OME-DEI 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fabrication of Stacked Logic Circuits for Printed Integrated Circuits 
Sub Title (in English)  
Keyword(1) Stacked Structure TFT  
Keyword(2) Logic Circuit  
Keyword(3) Silicone-resin  
Keyword(4) TIPS-pentacene  
Keyword(5) ZnO  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kazuhiro Kudo  
1st Author's Affiliation Chiba University (Chiba Univ.)
2nd Author's Name Isao Kodera  
2nd Author's Affiliation Chiba University (Chiba Univ.)
3rd Author's Name Hiroshi Yamauchi  
3rd Author's Affiliation Chiba University (Chiba Univ.)
4th Author's Name Shigekazu Kuniyoshi  
4th Author's Affiliation Chiba University (Chiba Univ.)
5th Author's Name Masatoshi Sakai  
5th Author's Affiliation Chiba University (Chiba Univ.)
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Speaker Author-1 
Date Time 2013-07-04 16:25:00 
Presentation Time 35 minutes 
Registration for OME 
Paper # OME2013-47 
Volume (vol) vol.113 
Number (no) no.115 
Page pp.25-30 
#Pages 6 
Date of Issue 2013-06-27 (OME) 

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