Paper Abstract and Keywords |
Presentation |
2013-07-04 10:55
[Invited Talk]
32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida (Fujitsu Lab. Ltd.), Hiroki Miyaoka (FSL), Masanori Hoshino (FMSL), Yoichi Koyanagi (Fujitsu Lab. Ltd.), Takuji Yamamoto (FLA), Sanroku Tsukamoto, Hirotaka Tamura (Fujitsu Lab. Ltd.) ICD2013-27 Link to ES Tech. Rep. Archives: ICD2013-27 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We present a 32Gb/s data-interpolator receiver for electrical chip-to-chip communications. The receiver front-end is clocked using a blind clock signal, which has a plesiochronous relation with the data. The phase alignment between the data and receiver clock is achieved by interpolating the input-signal samples obtained by using the blind clock. The receiver has a continuous-time linear equalizer and a 2-tap loop unrolled DFE using adjustable-threshold comparators. Implemented in 0.24mm2 in a 28-nm CMOS process, the total power consumption is 308mW from a 0.9V supply.
Keyword CDR, Data Interpolator, CTLE, DFE |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CDR / Data Interpolator / CTLE / DFE / High-Speed Interconnect / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 112, ICD2013-27, pp. 19-24, July 2013. |
Paper # |
ICD2013-27 |
Date of Issue |
2013-06-27 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2013-27 Link to ES Tech. Rep. Archives: ICD2013-27 |
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