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Paper Abstract and Keywords
Presentation 2013-07-12 15:45
3-Dimensional Phase Change Memory Enabling High Density and High Speed Storage
Takashi Kobayashi, Masaharu Kinoshita, Yoshitaka Sasago (Hitachi) MR2013-11
Abstract (in Japanese) (See Japanese page) 
(in English) A three-dimensional vertical chain-cell-type phase change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and each chain is selected by poly-Si diode. As a result of the configuration, the number of process steps, cell factor, and available design rule were reduced. Consequently, relative bit cost of the VCCPCM compared to 3-D NAND flash memory is reduced to 0.2. In addition, low-current reset operation with short pulse enables programming throughput as high as 1 GB/s. Selective read/write operation and 1 million endurance were confirmed by using 4-layer vertical chain cell.
Keyword (in Japanese) (See Japanese page) 
(in English) Three dimensional / Phase change memory / Storage / Stacked gate / Poly-Si diode / Bit cost / Programming throughput / Chain cell  
Reference Info. IEICE Tech. Rep., vol. 113, July 2013.
Paper #  
Date of Issue 2013-07-05 (MR) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF MR2013-11

Conference Information
Committee MRIS ITE-MMS  
Conference Date 2013-07-12 - 2013-07-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Chuo Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Solid State Memory, Media, etc. 
Paper Information
Registration To MRIS 
Conference Code 2013-07-MR-MMS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 3-Dimensional Phase Change Memory Enabling High Density and High Speed Storage 
Sub Title (in English)  
Keyword(1) Three dimensional  
Keyword(2) Phase change memory  
Keyword(3) Storage  
Keyword(4) Stacked gate  
Keyword(5) Poly-Si diode  
Keyword(6) Bit cost  
Keyword(7) Programming throughput  
Keyword(8) Chain cell  
1st Author's Name Takashi Kobayashi  
1st Author's Affiliation Hitachi, Ltd. (Hitachi)
2nd Author's Name Masaharu Kinoshita  
2nd Author's Affiliation Hitachi, Ltd. (Hitachi)
3rd Author's Name Yoshitaka Sasago  
3rd Author's Affiliation Hitachi, Ltd. (Hitachi)
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Speaker Author-1 
Date Time 2013-07-12 15:45:00 
Presentation Time 25 minutes 
Registration for MRIS 
Paper # MR2013-11 
Volume (vol) vol.113 
Number (no) no.127 
Page pp.31-34 
#Pages 4 
Date of Issue 2013-07-05 (MR) 

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