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Paper Abstract and Keywords
Presentation 2013-07-22 10:40
Design and evaluation of the 2-bit Bit-Slice Adder based on 10kA/cm^2 process
Kensuke Takata, Yuhi Hayakawa, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.) SCE2013-12
Abstract (in Japanese) (See Japanese page) 
(in English) A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm2 niobium advanced process, and demonstration of its high-speed operation.
Keyword (in Japanese) (See Japanese page) 
(in English) SFQ circuit / 10 kA/cm^2 process / 2-bit bit-slice adder / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 149, SCE2013-12, pp. 11-16, July 2013.
Paper # SCE2013-12 
Date of Issue 2013-07-15 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2013-12

Conference Information
Committee SCE  
Conference Date 2013-07-22 - 2013-07-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikaishinkou-kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Signal processing technologies and their applications, etc. 
Paper Information
Registration To SCE 
Conference Code 2013-07-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and evaluation of the 2-bit Bit-Slice Adder based on 10kA/cm^2 process 
Sub Title (in English)  
Keyword(1) SFQ circuit  
Keyword(2) 10 kA/cm^2 process  
Keyword(3) 2-bit bit-slice adder  
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1st Author's Name Kensuke Takata  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Yuhi Hayakawa  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Masamitsu Tanaka  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Akira Fujimaki  
4th Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker Author-1 
Date Time 2013-07-22 10:40:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2013-12 
Volume (vol) vol.113 
Number (no) no.149 
Page pp.11-16 
#Pages 6 
Date of Issue 2013-07-15 (SCE) 

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