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Paper Abstract and Keywords
Presentation 2013-08-01 18:00
Evaluation of Transient-Error-Tolerant Dependable Processors based on Multiplexed Registers
Naoki Midorikawa, Yoshifumi Koyama (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metropolitan Univ.) DC2013-20
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, highly reliable design technique for processors which have transient error tolerance are presented for various kind of architectures.
This paper examines the evaluation technique for such transient-error-tolerant dependable processors.
We leverage relatively small size of the state transition diagram for only describing the fault tolerant mechanisms on the basis of redundant configurations.
Specifically, fault tolerant processor for simultaneous occurrence of multiple transient faults presented by Marumoto et al. is focused on and the reliability evaluation model is discussed for its circuit scheme.
Keyword (in Japanese) (See Japanese page) 
(in English) transient fault / dependable processor / reliability evaluation / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 170, DC2013-20, pp. 21-25, Aug. 2013.
Paper # DC2013-20 
Date of Issue 2013-07-25 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2013-20

Conference Information
Committee DC CPSY  
Conference Date 2013-08-01 - 2013-08-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu-Kokusai-Kaigijyo 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To DC 
Conference Code 2013-07-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Transient-Error-Tolerant Dependable Processors based on Multiplexed Registers 
Sub Title (in English)  
Keyword(1) transient fault  
Keyword(2) dependable processor  
Keyword(3) reliability evaluation  
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1st Author's Name Naoki Midorikawa  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Yoshifumi Koyama  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
3rd Author's Name Masayuki Arai  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Satoshi Fukumoto  
4th Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
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Speaker Author-1 
Date Time 2013-08-01 18:00:00 
Presentation Time 30 minutes 
Registration for DC 
Paper # DC2013-20 
Volume (vol) vol.113 
Number (no) no.170 
Page pp.21-25 
#Pages 5 
Date of Issue 2013-07-25 (DC) 

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