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Paper Abstract and Keywords
Presentation 2013-08-02 17:00
Design of Variable Stages Pipeline Processor on Superscalar Processor
Tomoyuki Nakabayashi, Seiji Miyoshi, Takahiro Sasaki, Toshio Kondo (Mie Univ.) CPSY2013-27
Abstract (in Japanese) (See Japanese page) 
(in English) This paper designs a high performance and low energy superscalar processor using variable stages pipeline (VSP) technique. Because today's high-performance processors consume a large energy, power efficient processors are required. As one solutions, we propose VSP technique which dynamically modifies pipeline structure according to workload. If the workload is high, the VSP processor works as a high performance deep pipeline processor which is driven by high clock frequency. On the other hand, if the workload is low, the processor unifies some pipeline stages to make shallow pipeline processor, and it works as low energy pipeline processor using low clock frequency. Previously, we demonstrated the effectiveness of VSP technique by designing a single pipeline processor and evaluating energy consumption of fabricated VLSI chip. However, effectiveness of VSP technique for superscalar processor was shown by only simulation results. Therefore, as a first step to demonstrate effectiveness of VSP technique for superscalar, this paper designs superscalar processor using VSP technique.
Keyword (in Japanese) (See Japanese page) 
(in English) Low-energy processor / Processor architecture / Variable Stages Pipeline / Superscalar processor / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 169, CPSY2013-27, pp. 103-108, Aug. 2013.
Paper # CPSY2013-27 
Date of Issue 2013-07-25 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2013-27

Conference Information
Committee DC CPSY  
Conference Date 2013-08-01 - 2013-08-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu-Kokusai-Kaigijyo 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2013-08-DC-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Variable Stages Pipeline Processor on Superscalar Processor 
Sub Title (in English)  
Keyword(1) Low-energy processor  
Keyword(2) Processor architecture  
Keyword(3) Variable Stages Pipeline  
Keyword(4) Superscalar processor  
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1st Author's Name Tomoyuki Nakabayashi  
1st Author's Affiliation Mie University (Mie Univ.)
2nd Author's Name Seiji Miyoshi  
2nd Author's Affiliation Mie University (Mie Univ.)
3rd Author's Name Takahiro Sasaki  
3rd Author's Affiliation Mie University (Mie Univ.)
4th Author's Name Toshio Kondo  
4th Author's Affiliation Mie University (Mie Univ.)
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Speaker Author-2 
Date Time 2013-08-02 17:00:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2013-27 
Volume (vol) vol.113 
Number (no) no.169 
Page pp.103-108 
#Pages 6 
Date of Issue 2013-07-25 (CPSY) 

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