Paper Abstract and Keywords |
Presentation |
2013-08-02 14:25
[Invited Talk]
A 10th Generation 16-Core SPARC64 Processor for Mission-Critical UNIX Server Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi (Fujitsu), Yoichi Koyanagi (Fujitsu Laboratories), Ryuji Iwatsuki, Kazumi Hayasaka (Fujitsu), Taiki Uemura (Fujitsu Semiconductor), Gaku Itou, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada (Fujitsu) SDM2013-83 ICD2013-65 Link to ES Tech. Rep. Archives: SDM2013-83 ICD2013-65 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 10th generation SPARC64 processor is fabricated in enhanced 28nm CMOS process. It runs at 3.0GHz and contains 16 cores with 24MB shared L2 cache and system/DDR3/PCIe interfaces in the 588mm2 die area. Two steps read of GPR enables area reduction of 33% and out-of-order execution across register windows. A large SMP system of up to 64 CPUs with ccNUMA uses a newly developed 14.5Gb/s SerDes. Several techniques are used to mitigate SER. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
processor / SPARC / register file / SerDes / soft error / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 173, ICD2013-65, pp. 95-98, Aug. 2013. |
Paper # |
ICD2013-65 |
Date of Issue |
2013-07-25 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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SDM2013-83 ICD2013-65 Link to ES Tech. Rep. Archives: SDM2013-83 ICD2013-65 |
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