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| Presentation | 2013-09-19 09:00 A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.)  RECONF2013-26 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Leakage power is a serious problem especially for accerelators which use a large size Processing Ele- ment (PE) array. Here, a low power reconfigurable accelerator called Cool Mega Array (CMA) with back-gate bias control (CMA-bb) is implemented and evaluated. In CMA-bb, the back-gate bias of the microcontroller and PE array can be controlled independently. In the idle mode, reverse bias is given to the both parts to suppress the leakage current. When high performance is required, forward bias is used to increase the clock frequency. For simple applications, the operational power can be suppressed by using reverse bias only in the PE array. On the other hand, by giving forward bias to the PE array, the performance can be increased with a small increases of the power in the computation centric applications. The real chip is implemented with a 65nm experimental process for low leakage applications. The evaluation results show that the leakage current can be suppressed to 300μA by using the reverse bias. The operational frequency is increased from 39MHz to 50MHz with up to 21% increase of operational power by using the forward bias. For simple applications, 8% to 9.4% of operational power is saved by giving reverse bias only to the PE array. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Corase Grained Reconfigurable Processor / Leakage Power Reduction / Back-gate Bias Control / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 221, RECONF2013-26, pp. 37-42, Sept. 2013. | |
| Paper # | RECONF2013-26 | |
| Date of Issue | 2013-09-11 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2013-26 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2013-09-18 - 2013-09-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Japan Advanced Institute of Science and Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2013-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique |
| Sub Title (in English) | |
| Keyword(1) | Corase Grained Reconfigurable Processor |
| Keyword(2) | Leakage Power Reduction |
| Keyword(3) | Back-gate Bias Control |
| Keyword(4) | |
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| 1st Author's Name | Hongliang Su |
| 1st Author's Affiliation | Keio niversity (Keio Univ.) |
| 2nd Author's Name | Weihan Wang |
| 2nd Author's Affiliation | Keio niversity (Keio Univ.) |
| 3rd Author's Name | Hideharu Amano |
| 3rd Author's Affiliation | Keio niversity (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-09-19 09:00:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2013-26 |
| Volume (vol) | vol.113 |
| Number (no) | no.221 |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2013-09-11 (RECONF) |
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