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Paper Abstract and Keywords
Presentation 2013-10-03 11:10
TMR execution on SmartCore system for dependable many-core processors
Ryosuke Sasakawa, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-32
Abstract (in Japanese) (See Japanese page) 
(in English) In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR(Dual Modular Redundant) mechanism by employing inherent redundancies of PEs in many-core processors.
We also have proposed a multifunction on-chip router architecture that has additional capabilities to support DMR execution such as packet rendezvous and packet comparison.
In this paper, we propose packet traverse rule and a multifunction router in order to support TMR(Triple Modular Redundant) execution.
The packet traverse rule and the multifunction router for TMR execution is based on that of DMR execution.
We evaluated the network performance in TMR execution by using several common network traffic patterns.
The evaluation result shows that the increase of latency by TMR execution is about twice as long as the increase of latency by DMR execution.
We also confirm that there is the allocation of TMR node parties which doesn’t show worse throughput.
Keyword (in Japanese) (See Japanese page) 
(in English) Network on Chip / Many-core Processor / Triple Modular Redundancy / Network Performance / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 234, CPSY2013-32, pp. 7-12, Oct. 2013.
Paper # CPSY2013-32 
Date of Issue 2013-09-26 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY  
Conference Date 2013-10-03 - 2013-10-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Makuhari Messe 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Computing for User Supporting, etc -from personal devices to smart cities- 
Paper Information
Registration To CPSY 
Conference Code 2013-10-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) TMR execution on SmartCore system for dependable many-core processors 
Sub Title (in English)  
Keyword(1) Network on Chip  
Keyword(2) Many-core Processor  
Keyword(3) Triple Modular Redundancy  
Keyword(4) Network Performance  
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1st Author's Name Ryosuke Sasakawa  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Shimpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Kenji Kise  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker Author-1 
Date Time 2013-10-03 11:10:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2013-32 
Volume (vol) vol.113 
Number (no) no.234 
Page pp.7-12 
#Pages 6 
Date of Issue 2013-09-26 (CPSY) 

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