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Paper Abstract and Keywords
Presentation 2013-10-07 10:30
A Memory Based Filed Programmable Device for Energy saving MCUs
Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) VLD2013-46 ICD2013-70 IE2013-46
Abstract (in Japanese) (See Japanese page) 
(in English) A Field Programmable Sequencer and memory (FPSM), which is an embedded memory based programmable peripherals for Micro Controller Units, was proposed in architecture level. The FPSM functions as not only memories but also as finite autonomous state transition controls without CPU. In this paper, concept and architecture of FPSM, and an implementation on an FPGA is described. The FPGA operates at the maximum frequency of 50 MHz. Correct operations of fundamental peripherals such as timers, shifters, serial receivers/transmitters, FIFOs and Pulse Width Modulations (PWM) are verified.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / MCU / Memory / Peripheral functions / Programmable devices / Sequencer / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 235, VLD2013-46, pp. 1-6, Oct. 2013.
Paper # VLD2013-46 
Date of Issue 2013-09-30 (VLD, ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-46 ICD2013-70 IE2013-46

Conference Information
Committee IE ICD VLD IPSJ-SLDM  
Conference Date 2013-10-07 - 2013-10-08 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2013-10-IE-ICD-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Memory Based Filed Programmable Device for Energy saving MCUs 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) MCU  
Keyword(3) Memory  
Keyword(4) Peripheral functions  
Keyword(5) Programmable devices  
Keyword(6) Sequencer  
Keyword(7)  
Keyword(8)  
1st Author's Name Tetsuya Matsumura  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Yoshifumi Kawamura  
2nd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
3rd Author's Name Naoya Okada  
3rd Author's Affiliation Kanazawa University (Kanazawa Univ.)
4th Author's Name Kazutami Arimoto  
4th Author's Affiliation Okayama Prefectual University (Okayama Prefectual Univ.)
5th Author's Name Hiroshi Makino  
5th Author's Affiliation Osaka Institute of Technology (OIT)
6th Author's Name Yoshio Matsuda  
6th Author's Affiliation Kanazawa University (Kanazawa Univ.)
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Speaker Author-1 
Date Time 2013-10-07 10:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-46, ICD2013-70, IE2013-46 
Volume (vol) vol.113 
Number (no) no.235(VLD), no.236(ICD), no.237(IE) 
Page pp.1-6 
#Pages 6 
Date of Issue 2013-09-30 (VLD, ICD, IE) 

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