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| Presentation | 2013-10-24 15:45 Design of an FPGA-Based FDTD Accelerator Using OpenCL Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)  EMCJ2013-73 MW2013-113 EST2013-65 Link to ES Tech. Rep. Archives: MW2013-113 EST2013-65 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | High-performance computing systems with dedicated hardware on FPGAs can achieve power efficient computations compared with CPUs and GPUs. However, the hardware design on FPGAs needs more time than the software design on CPUs and GPUs. We designed an FDTD hardware accelerator using the OpenCL compiler for FPGA in this paper. Since it is possible to create hardware automatically from the OpenCL code by using this compiler, we can implement applications on FPGAs in a short time compared with the design with a hardware description language. According to the result of the implementation of the FDTD accelerator on the FPGA, the processing speed is faster than CPU. Moreover, the power consumption is about one-tenth of GPU. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | OpenCL / FPGA / FDTD method / Hardware accelerator / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 261, EST2013-65, pp. 73-76, Oct. 2013. | |
| Paper # | EST2013-65 | |
| Date of Issue | 2013-10-17 (EMCJ, MW, EST) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | EMCJ2013-73 MW2013-113 EST2013-65 Link to ES Tech. Rep. Archives: MW2013-113 EST2013-65 |
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| Conference Information | |
| Committee | EMCJ IEE-EMC MW EST |
| Conference Date | 2013-10-24 - 2013-10-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tohoku Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | EMC, Micro wave, Electromagnetic analysis, etc. |
| Paper Information | |
| Registration To | EST |
| Conference Code | 2013-10-EMCJ-EMC-MW-EST |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of an FPGA-Based FDTD Accelerator Using OpenCL |
| Sub Title (in English) | |
| Keyword(1) | OpenCL |
| Keyword(2) | FPGA |
| Keyword(3) | FDTD method |
| Keyword(4) | Hardware accelerator |
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| 1st Author's Name | Yasuhiro Takei |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Hasitha Muthumala Waidyasooriya |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Masanori Hariyama |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 4th Author's Name | Michitaka Kameyama |
| 4th Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-10-24 15:45:00 |
| Presentation Time | 25 minutes |
| Registration for | EST |
| Paper # | EMCJ2013-73, MW2013-113, EST2013-65 |
| Volume (vol) | vol.113 |
| Number (no) | no.259(EMCJ), no.260(MW), no.261(EST) |
| Page | pp.73-76 |
| #Pages | 4 |
| Date of Issue | 2013-10-17 (EMCJ, MW, EST) |
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