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Paper Abstract and Keywords
Presentation 2013-11-14 15:00
[Invited Talk] Analysis of Low-Frequency Noise in Silicon Tri-Gate Nanowire Transistors
Masumi Saitoh, Kensuke Ota, Chika Tanaka, Toshinori Numata (Toshiba) SDM2013-104
Abstract (in Japanese) (See Japanese page) 
(in English) We systematically study the channel size dependence of 1/f noise in silicon tri-gate nanowire transistors by measuring a large number of samples with various parameters such as nanowire width (WNW), height (HNW), and number (NNW). For a wide range of Lg, WNW and HNW, the universal line appears in the normalized noise (SId/Id2) - 1/(LgWeff) plot, which can be explained by conventional carrier number fluctuations. But, the noise of narrow nanowire transistors (down to 10nm) rapidly increases with 1/WNW due to bottleneck effects, where an electron in a single trap on the nanowire channel raises the potential of the whole channel along WNW and causes large current noise. Also, the noise of short-Lg Tr. (down to 15nm) saturates due to the reduction of channel area and a number of traps.
Keyword (in Japanese) (See Japanese page) 
(in English) nanowire / tri-gate / low-frequency noise / carrier number fluctuation / trap / parasitic resistance / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 296, SDM2013-104, pp. 27-30, Nov. 2013.
Paper # SDM2013-104 
Date of Issue 2013-11-07 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SDM  
Conference Date 2013-11-14 - 2013-11-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process, Device, Circuit Simulations, etc. 
Paper Information
Registration To SDM 
Conference Code 2013-11-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Low-Frequency Noise in Silicon Tri-Gate Nanowire Transistors 
Sub Title (in English)  
Keyword(1) nanowire  
Keyword(2) tri-gate  
Keyword(3) low-frequency noise  
Keyword(4) carrier number fluctuation  
Keyword(5) trap  
Keyword(6) parasitic resistance  
Keyword(7)  
Keyword(8)  
1st Author's Name Masumi Saitoh  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Kensuke Ota  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name Chika Tanaka  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
4th Author's Name Toshinori Numata  
4th Author's Affiliation Toshiba Corporation (Toshiba)
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Speaker Author-1 
Date Time 2013-11-14 15:00:00 
Presentation Time 50 minutes 
Registration for SDM 
Paper # SDM2013-104 
Volume (vol) vol.113 
Number (no) no.296 
Page pp.27-30 
#Pages 4 
Date of Issue 2013-11-07 (SDM) 

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