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| Presentation | 2013-11-27 10:20 Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM Shintaro Ukai, Tsunato Nakai, Toshiki Kitamura, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.)  CPM2013-111 ICD2013-88 Link to ES Tech. Rep. Archives: CPM2013-111 ICD2013-88 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Tamper-resistant devices require to protect cryptographic circuit from side-channel attacks such as power analysis (PA) and electromagnetic analysis (EMA). This paper proposes hybrid masking dual-rail ROM (HMDR-ROM) scheme as a countermeasure against side-channel attacks. The HMDR-ROM scheme combines IO-Masked Dual-Rail ROM with both additive and multiplicative masking technique. The IO-masked dual-rail ROM consumes constant power regardless of input/output values. And, these masking techniques are used to hide correlations between the secret key and information leakages. A prototype AES chip was designed and fabricated with a 0.18μm CMOS technology. We confirm that the proposed scheme achieves low area and low power compared with other countermeasures, and the strong resistance against PA/EMA attacks. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Side-Channel Attack / AES / CPA / CEMA / Dual-Rail ROM / Hybrid Mask / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 323, ICD2013-88, pp. 19-24, Nov. 2013. | |
| Paper # | ICD2013-88 | |
| Date of Issue | 2013-11-20 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2013-111 ICD2013-88 Link to ES Tech. Rep. Archives: CPM2013-111 ICD2013-88 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2013-11-27 - 2013-11-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2013 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM |
| Sub Title (in English) | |
| Keyword(1) | Side-Channel Attack |
| Keyword(2) | AES |
| Keyword(3) | CPA |
| Keyword(4) | CEMA |
| Keyword(5) | Dual-Rail ROM |
| Keyword(6) | Hybrid Mask |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Shintaro Ukai |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Tsunato Nakai |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Toshiki Kitamura |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Takaya Kubota |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 5th Author's Name | Mitsuru Shiozaki |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 6th Author's Name | Takeshi Fujino |
| 6th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-11-27 10:20:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | CPM2013-111, ICD2013-88 |
| Volume (vol) | vol.113 |
| Number (no) | no.322(CPM), no.323(ICD) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2013-11-20 (CPM, ICD) |
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