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Paper Abstract and Keywords
Presentation 2013-11-27 14:00
[Invited Talk] Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi) VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41
Abstract (in Japanese) (See Japanese page) 
(in English) To improve the performance of 3D-stacking using TSV interconnects, circuit techniques were developed. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An “embedded TSV“ design for the shorter on-chip wirings was also devised. Z-axis transmission performance was the highest, namely, 15 Tbps/W. TSV circuit model is proposed for circuit design of 3D transmission. Moreover, to reduce the clock skew between the stacked layers arising from global process variations, a 3D clock-synchronization scheme using a reference clock via TSVs was developed. The clock skew between two layers was reduced by 60% using the new clock scheme. We present the first demonstration of two stacked FPGA layers by using wafer-to-wafer via-last Cu-TSV process
Keyword (in Japanese) (See Japanese page) 
(in English) TSV / 3D / FPGA / Synchronization scheme / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 323, ICD2013-94, pp. 55-58, Nov. 2013.
Paper # ICD2013-94 
Date of Issue 2013-11-20 (VLD, CPM, ICD, CPSY, DC, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Circuit design for 3D-stacking using TSV interconnects 
Sub Title (in English)  
Keyword(1) TSV  
Keyword(2) 3D  
Keyword(3) FPGA  
Keyword(4) Synchronization scheme  
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1st Author's Name Kenichi Osada  
1st Author's Affiliation Hitachi, Ltd. (Hitachi)
2nd Author's Name Futoshi Furuta  
2nd Author's Affiliation Hitachi, Ltd. (Hitachi)
3rd Author's Name Kenichi Takeda  
3rd Author's Affiliation Hitachi, Ltd. (Hitachi)
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Speaker Author-1 
Date Time 2013-11-27 14:00:00 
Presentation Time 40 minutes 
Registration for ICD 
Paper # VLD2013-73, CPM2013-117, ICD2013-94, CPSY2013-58, DC2013-39, RECONF2013-41 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.322(CPM), no.323(ICD), no.324(CPSY), no.321(DC), no.325(RECONF) 
Page pp.93-96(VLD), pp.55-58(CPM), pp.55-58(ICD), pp.1-4(CPSY), pp.93-96(DC), pp.13-16(RECONF) 
#Pages 4 
Date of Issue 2013-11-20 (VLD, CPM, ICD, CPSY, DC, RECONF) 

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