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Paper Abstract and Keywords
Presentation 2013-11-28 14:10
An inverter block construction method to reduce test data volume on BAST
Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute) VLD2013-85 DC2013-51
Abstract (in Japanese) (See Japanese page) 
(in English) BAST is one of technique to reduce the amount of test data while maintaining the high test quality using built-in self test and deterministic test generation.On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns.BAST code which is test data on BAST is composed of shift instructions and bit-flipping instructions.The number of shift instructions depends on the number of deterministic patterns and scan chain length, and the number of bit-flipping instructions depends on the number of conflicts between deterministic patterns and pseudo random patterns.In this paper,we propose a method of the inverter block contruction on BAST to reduce the number of bit-flipping instructions.The reduction ratios for the number of bit-flipping instructions are evaluated for ISCAS'89 benchmark circuits and ITC'99 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) BAST architecture / bit-flipping instructions / inverter blocks / scan chains / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 321, DC2013-51, pp. 171-176, Nov. 2013.
Paper # DC2013-51 
Date of Issue 2013-11-20 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An inverter block construction method to reduce test data volume on BAST 
Sub Title (in English)  
Keyword(1) BAST architecture  
Keyword(2) bit-flipping instructions  
Keyword(3) inverter blocks  
Keyword(4) scan chains  
Keyword(5)  
Keyword(6)  
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Keyword(8)  
1st Author's Name Marika Tanaka  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Hiroshi Yamazaki  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon University (Nihon Univ)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyushu University (Kyushu Univ)
5th Author's Name Masayuki Arai  
5th Author's Affiliation Nihon University (Nihon Univ)
6th Author's Name Michinobu Nakao  
6th Author's Affiliation Yomiuri institute of technology (Yomiuri Institute)
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Speaker Author-1 
Date Time 2013-11-28 14:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2013-85, DC2013-51 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.321(DC) 
Page pp.171-176 
#Pages 6 
Date of Issue 2013-11-20 (VLD, DC) 

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