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Paper Abstract and Keywords
Presentation 2013-11-28 14:35
Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) RECONF2013-55
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we evaluate some logic and interconnection structures for MPLD, which is a basic architecture
for reconfigurable logic devices composed of only memory cells and wires between them, by placing and
routing benchmark circuits on the structures. The goal of this evaluation is to find good structures for MPLD
that can efficiently map larger circuits using smaller chip area. For the experiments, we implemented an architecture-
independent placement and routing tool for MPLD by eliminating the architecture-dependent term in the cost
function of an existing placement and routing tool for MPLD.
Keyword (in Japanese) (See Japanese page) 
(in English) MPLD / PLD / FPGA / architecture / Place-and-Route / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 325, RECONF2013-55, pp. 87-92, Nov. 2013.
Paper # RECONF2013-55 
Date of Issue 2013-11-20 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-55

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD 
Sub Title (in English)  
Keyword(1) MPLD  
Keyword(2) PLD  
Keyword(3) FPGA  
Keyword(4) architecture  
Keyword(5) Place-and-Route  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Tomoya Yamashita  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ)
2nd Author's Name Masato Inagi  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ)
3rd Author's Name Kazuya Tanigawa  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ)
4th Author's Name Tetsuo Hironaka  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ)
5th Author's Name Takashi Ishiguro  
5th Author's Affiliation TAIYO YUDEN CO.LTD (TAIYO YUDEN)
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Speaker Author-1 
Date Time 2013-11-28 14:35:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2013-55 
Volume (vol) vol.113 
Number (no) no.325 
Page pp.87-92 
#Pages
Date of Issue 2013-11-20 (RECONF) 


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