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Paper Abstract and Keywords
Presentation 2013-11-29 08:55
A Method of LFSR Seed Generation for Delay Fault BIST
Taro Honda, Satoshi Ohtake (Oita Univ.) VLD2013-92 DC2013-58
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a method to generate LFSR seeds for delay fault BIST. A conventional way to generate seeds is the following. A test pattern for a fault is first generated and the pattern is then converted into a seed. However, the test pattern may not always be converted into a seed even if a seed exists for the fault. In such cases, fault coverage loss may occur. To solve the problem, the authors have proposed a method to generate LFSR seeds for scan-based BIST for static faults using constrained ATPG. In this method, the LFSR is expanded into a time expansion model, which is a combinational circuit called an XOR network, as test generation constraint circuitry and it is connected to the combinational part of a circuit under test to form a seed generation model. Seeds can be generated directly for faults in the combinational part by applying an ATPG to the seed generation model. In this paper, the method is expanded to test delay faults under the launch-off-capture (LoC) scheme. In the LoC scheme, an internal state is used as the second pattern of a two pattern test. To support this, seed generation methods using two time expansion model and using circuitry selecting the outputs of XOR network and the internal states are proposed in this paper. The effectiveness of the latter proposed method is shown through experiments using ITC'99 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) BIST / delay fault / seed generation / constrained test generation / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 321, DC2013-58, pp. 227-231, Nov. 2013.
Paper # DC2013-58 
Date of Issue 2013-11-20 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-92 DC2013-58

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Method of LFSR Seed Generation for Delay Fault BIST 
Sub Title (in English)  
Keyword(1) BIST  
Keyword(2) delay fault  
Keyword(3) seed generation  
Keyword(4) constrained test generation  
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1st Author's Name Taro Honda  
1st Author's Affiliation Oita University (Oita Univ.)
2nd Author's Name Satoshi Ohtake  
2nd Author's Affiliation Oita University (Oita Univ.)
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Speaker Author-1 
Date Time 2013-11-29 08:55:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2013-92, DC2013-58 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.321(DC) 
Page pp.227-231 
#Pages 5 
Date of Issue 2013-11-20 (VLD, DC) 

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