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Paper Abstract and Keywords
Presentation 2013-11-29 13:20
NoC routers using the marching memory through type
Ryota Yasudo, Takahiro Kagami, Hideharu Amano (Keio Univ.), Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu (Renesas), Tadao Nakamura (Keio Univ.) CPSY2013-71
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a NoC(Network-on Chip) router using the marching memory through type in order to reduce the power consumption of the router. The marching memory through type is a memory of small capacity by low power at high speed, whose data structure is FIFO. In this paper, we designed a NoC router using this memory in its input buffer, and evaluated its power consumption. As a result, we reduced the power by 28.8 percent compared with the oridinal one. If we take account of data dependency, we can achieve more reduction.
Keyword (in Japanese) (See Japanese page) 
(in English) Network-on-Chip(NoC) / marching memory through type / router / input buffer / low power / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 324, CPSY2013-71, pp. 71-76, Nov. 2013.
Paper # CPSY2013-71 
Date of Issue 2013-11-20 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) NoC routers using the marching memory through type 
Sub Title (in English)  
Keyword(1) Network-on-Chip(NoC)  
Keyword(2) marching memory through type  
Keyword(3) router  
Keyword(4) input buffer  
Keyword(5) low power  
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Keyword(8)  
1st Author's Name Ryota Yasudo  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Takahiro Kagami  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Hideharu Amano  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Yasunobu Nakase  
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5th Author's Name Masashi Watanabe  
5th Author's Affiliation Renesas Electronics (Renesas)
6th Author's Name Tsukasa Oishi  
6th Author's Affiliation Renesas Electronics (Renesas)
7th Author's Name Toru Shimizu  
7th Author's Affiliation Renesas Electronics (Renesas)
8th Author's Name Tadao Nakamura  
8th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2013-11-29 13:20:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2013-71 
Volume (vol) vol.113 
Number (no) no.324 
Page pp.71-76 
#Pages 6 
Date of Issue 2013-11-20 (CPSY) 

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