Paper Abstract and Keywords |
Presentation |
2013-11-29 10:25
Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis Shingo Kusakabe, Tomohito Toyama, Kenshu Seto (Tokyo City Univ.) VLD2013-95 DC2013-61 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is very important. Existing loop pipelining techniques, however, pessimistically assumes that dependences whose the occurrence can be determined only at runtime always occur, resulting in increased IIs. To address this issue, recent work achieves reduced II by a source code transformation which introduces runtime dependence analysis and pipeline stall when dependences actually occur. Unfortunately, the previous work suffers from the increased execution cycles by frequent pipeline stall under the frequent occurrences of dependences. In this paper, we propose a technique to reduce IIs in which data written to memories are also written to registers for such RAW dependences. In our technique, registers which are faster than memories are accessed when the RAW dependences occur. Since the proposed approach achieved 1.6x speedups with 1.2x area increase on average for 3 examples, so we conclude that the proposed technique is effective for synthesizing high-speed circuits with loop pipelining. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
high level synthesis / loop pipelining / memory accesses / RAW dependence / forwarding / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 320, VLD2013-95, pp. 245-249, Nov. 2013. |
Paper # |
VLD2013-95 |
Date of Issue |
2013-11-20 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2013-95 DC2013-61 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2013-11-27 - 2013-11-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
|
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2013 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis |
Sub Title (in English) |
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Keyword(1) |
high level synthesis |
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loop pipelining |
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memory accesses |
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RAW dependence |
Keyword(5) |
forwarding |
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1st Author's Name |
Shingo Kusakabe |
1st Author's Affiliation |
Tokyo City University (Tokyo City Univ.) |
2nd Author's Name |
Tomohito Toyama |
2nd Author's Affiliation |
Tokyo City University (Tokyo City Univ.) |
3rd Author's Name |
Kenshu Seto |
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Tokyo City University (Tokyo City Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-11-29 10:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2013-95, DC2013-61 |
Volume (vol) |
vol.113 |
Number (no) |
no.320(VLD), no.321(DC) |
Page |
pp.245-249 |
#Pages |
5 |
Date of Issue |
2013-11-20 (VLD, DC) |
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