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| Presentation | 2014-01-24 15:55 Trilayer junction technology for superconducting quantum integrated circuit Masaaki Maezawa, Tetsuro Satoh, Yoshiji Noguchi, Masashi Yamagishi, Mutsuo Hidaka, Tsuyoshi Horikawa (AIST)  SCE2013-57 Link to ES Tech. Rep. Archives: SCE2013-57 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We present a fabrication technology of deep-submicron Josephson junctions for scalable integration of superconducting quantum-bit circuits, which enables a practical superconducting quantum computer. A self-aligned trilayer process for Al/AlOx/Al junctions has been developed by using a chemical mechanical polishing (CMP) technique. Taking account of the chemical and mechanical fragility of Al thin films, we have optimized the junction process and successfully fabricated 100-nm-scale junctions applicable to integrated superconducting quantum bits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Quantum Information Processing / Josephson Junction / Superconducting Integrated Circuit / Planarization / Small Junction / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 401, SCE2013-57, pp. 129-134, Jan. 2014. | |
| Paper # | SCE2013-57 | |
| Date of Issue | 2014-01-16 (SCE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SCE2013-57 Link to ES Tech. Rep. Archives: SCE2013-57 |
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| Conference Information | |
| Committee | SCE |
| Conference Date | 2014-01-23 - 2014-01-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikaishinkou-kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Thin film, device technologies and their applications, etc. |
| Paper Information | |
| Registration To | SCE |
| Conference Code | 2014-01-SCE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Trilayer junction technology for superconducting quantum integrated circuit |
| Sub Title (in English) | |
| Keyword(1) | Quantum Information Processing |
| Keyword(2) | Josephson Junction |
| Keyword(3) | Superconducting Integrated Circuit |
| Keyword(4) | Planarization |
| Keyword(5) | Small Junction |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masaaki Maezawa |
| 1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 2nd Author's Name | Tetsuro Satoh |
| 2nd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 3rd Author's Name | Yoshiji Noguchi |
| 3rd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 4th Author's Name | Masashi Yamagishi |
| 4th Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 5th Author's Name | Mutsuo Hidaka |
| 5th Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 6th Author's Name | Tsuyoshi Horikawa |
| 6th Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
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| Speaker | Author-1 |
| Date Time | 2014-01-24 15:55:00 |
| Presentation Time | 25 minutes |
| Registration for | SCE |
| Paper # | SCE2013-57 |
| Volume (vol) | vol.113 |
| Number (no) | no.401 |
| Page | pp.129-134 |
| #Pages | 6 |
| Date of Issue | 2014-01-16 (SCE) |
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