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Paper Abstract and Keywords
Presentation 2014-01-28 10:25
A Storing and Regenerating Signal Information in a Scalable Hardware System
Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60
Abstract (in Japanese) (See Japanese page) 
(in English) In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating frequency sometimes occurs. For such a problem, though circuit partitioning is applied to multiple LSIs, conventional communication of signal information including a clock signal among partitioned circuits is difficult to be applied for acceleration due to sacrifice of an operating frequency. To overcome such problems, we have proposed a scalable hardware mechanism with keeping its operation frequency and allowing communicating signal information among partitioned circuits. In this paper, a storing and regenerating signal information which are needed in burst transferring signal information among partitioned circuits as well as the concept of the scalable circuit hardware mechanism is described.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Circuit Partitioning / Synchronization / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 417, CPSY2013-77, pp. 25-30, Jan. 2014.
Paper # CPSY2013-77 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-106 CPSY2013-77 RECONF2013-60

Conference Information
Committee IPSJ-SLDM CPSY RECONF VLD  
Conference Date 2014-01-28 - 2014-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2014-01-SLDM-CPSY-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Storing and Regenerating Signal Information in a Scalable Hardware System 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Circuit Partitioning  
Keyword(3) Synchronization  
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1st Author's Name Yusuke Katoh  
1st Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech)
2nd Author's Name Daisuke Watanabe  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech)
3rd Author's Name Hironori Nakajo  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech)
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Speaker Author-1 
Date Time 2014-01-28 10:25:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # VLD2013-106, CPSY2013-77, RECONF2013-60 
Volume (vol) vol.113 
Number (no) no.416(VLD), no.417(CPSY), no.418(RECONF) 
Page pp.25-30 
#Pages 6 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 

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