Paper Abstract and Keywords |
Presentation |
2014-01-28 11:40
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) VLD2013-109 CPSY2013-80 RECONF2013-63 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been proposed.
However, the size of circuits synthesized by this algorithm tends to be large because it assumes QDI delay model. Yoshitake proposed a reduction method using a characteristic of a maximum delay loop in a dependency graph under SDI delay model.
In this paper, we improve the method by extending the application range to dependency graphs that have multiple maximum delay loop. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous circuits / Dependency graphs / QDI delay model / SDI delay model / Maximum delay loop / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 417, CPSY2013-80, pp. 43-48, Jan. 2014. |
Paper # |
CPSY2013-80 |
Date of Issue |
2014-01-21 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2013-109 CPSY2013-80 RECONF2013-63 |
Conference Information |
Committee |
IPSJ-SLDM CPSY RECONF VLD |
Conference Date |
2014-01-28 - 2014-01-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
CPSY |
Conference Code |
2014-01-SLDM-CPSY-RECONF-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption |
Sub Title (in English) |
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Keyword(1) |
Asynchronous circuits |
Keyword(2) |
Dependency graphs |
Keyword(3) |
QDI delay model |
Keyword(4) |
SDI delay model |
Keyword(5) |
Maximum delay loop |
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1st Author's Name |
Tomoya Tasaki |
1st Author's Affiliation |
Okayama University (Okayama Univ.) |
2nd Author's Name |
Hiroto Kagotani |
2nd Author's Affiliation |
Okayama University (Okayama Univ.) |
3rd Author's Name |
Yuji Sugiyama |
3rd Author's Affiliation |
Okayama University (Okayama Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-01-28 11:40:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
VLD2013-109, CPSY2013-80, RECONF2013-63 |
Volume (vol) |
vol.113 |
Number (no) |
no.416(VLD), no.417(CPSY), no.418(RECONF) |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2014-01-21 (VLD, CPSY, RECONF) |
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