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| Presentation | 2014-01-28 10:50 Hardware Expansion Protocol in a Scalable Hardware System Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.)  VLD2013-107 CPSY2013-78 RECONF2013-61 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available number of logic cells and LUTs as well as decreasing operating frequency due to their growing utilization in a current FPGA are increasing limit the size of implemented hardware. Against the problem, a large sized circuit is partitioned and imlemented into several FPGAs. In this case communicating signal information among FPGAs is important. Focusing on the communication, we have introduced a Scalable Hardware System which realizes efficient partitioned circuits as well as Hardware Expansion Protocol to support the system. In this paper, our proposed Hardware Expansion Protocol is implemented between FPGAs and evaluated with an AES circuit. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / Circuit Partitioning / Multi-FPGA / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 417, CPSY2013-78, pp. 31-36, Jan. 2014. | |
| Paper # | CPSY2013-78 | |
| Date of Issue | 2014-01-21 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-107 CPSY2013-78 RECONF2013-61 |
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| Conference Information | |
| Committee | IPSJ-SLDM CPSY RECONF VLD |
| Conference Date | 2014-01-28 - 2014-01-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2014-01-SLDM-CPSY-RECONF-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Expansion Protocol in a Scalable Hardware System |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Circuit Partitioning |
| Keyword(3) | Multi-FPGA |
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| 1st Author's Name | Daisuke Watanabe |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
| 2nd Author's Name | Yusuke Katoh |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
| 3rd Author's Name | Hironori Nakajo |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
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| Speaker | Author-1 |
| Date Time | 2014-01-28 10:50:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | VLD2013-107, CPSY2013-78, RECONF2013-61 |
| Volume (vol) | vol.113 |
| Number (no) | no.416(VLD), no.417(CPSY), no.418(RECONF) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2014-01-21 (VLD, CPSY, RECONF) |
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