Paper Abstract and Keywords |
Presentation |
2014-01-29 16:45
Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The accelerator is tightly coupled with a CPU; it watches the program counter of the CPU to start execution when the specified addresses are reached, and it returns control to the CPU by rewriting the program counter. It also shares data with CPU by directly accessing the register file and the main memory. In our method, operations for accessing the register file and the program counter are added to a control dataflow graph (CDFG) derived from the specified machine code segments, which is fed into a high-level synthesis back-end. CDFGs are optimized by 1) removing redundant register file access operations based on dataflow analysis of the entire machine program, and 2) by scheduling operations considering the pipeline status of the CPU. The proposed method has been implemented on top of the ACAP high-level synthesizer. The experimental results show that the entire program execution speed was accelerated by 1.5 to 3.0 times at the cost of 50% to 140% increase in the hardware size. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-Level Synthesis / machine language program / hardware/software codesign / hardware accelerator tightly coupled with CPU / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 416, VLD2013-133, pp. 185-190, Jan. 2014. |
Paper # |
VLD2013-133 |
Date of Issue |
2014-01-21 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2013-133 CPSY2013-104 RECONF2013-87 |
Conference Information |
Committee |
IPSJ-SLDM CPSY RECONF VLD |
Conference Date |
2014-01-28 - 2014-01-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2014-01-SLDM-CPSY-RECONF-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU |
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Keyword(1) |
High-Level Synthesis |
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machine language program |
Keyword(3) |
hardware/software codesign |
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hardware accelerator tightly coupled with CPU |
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1st Author's Name |
Shimpei Tamura |
1st Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
2nd Author's Name |
Nagisa Ishiura |
2nd Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
3rd Author's Name |
Hiroyuki Kanbara |
3rd Author's Affiliation |
ASTEM RI/KYOTO (ASTEM) |
4th Author's Name |
Hiroyuki Tomiyama |
4th Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-01-29 16:45:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2013-133, CPSY2013-104, RECONF2013-87 |
Volume (vol) |
vol.113 |
Number (no) |
no.416(VLD), no.417(CPSY), no.418(RECONF) |
Page |
pp.185-190 |
#Pages |
6 |
Date of Issue |
2014-01-21 (VLD, CPSY, RECONF) |
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