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| Presentation | 2014-01-29 13:20 A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT)  VLD2013-126 CPSY2013-97 RECONF2013-80 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, a scalable and reconfigurable multi-FPGA system has been proposed which consists of two or more boards, each of which consists of one router FPGA chip and five general-purpose FPGA chips. The five general-purpose FPGA chips are connected to form a ring and the router FPGA chip performs inter-board communications. How to map a task graph onto such a multi-FPGA system is one of the challenging problems. In this paper, we propose a task mapping algorithm for a multi-FPGA system. Since the multi-FPGA system has a hierarchical structure, we have to find out {it locality/} in a given task graph. In our proposed algorithm, we focus on the communication rate between tasks and try to assign the ones with many communications between them to the same FPGA chip one by one. Experimental results demonstrate the effectiveness of our proposed algorithm. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | task mapping / task graph / multi-FPGA systems / network-on-chip / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 416, VLD2013-126, pp. 143-148, Jan. 2014. | |
| Paper # | VLD2013-126 | |
| Date of Issue | 2014-01-21 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-126 CPSY2013-97 RECONF2013-80 |
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| Conference Information | |
| Committee | IPSJ-SLDM CPSY RECONF VLD |
| Conference Date | 2014-01-28 - 2014-01-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-01-SLDM-CPSY-RECONF-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems |
| Sub Title (in English) | |
| Keyword(1) | task mapping |
| Keyword(2) | task graph |
| Keyword(3) | multi-FPGA systems |
| Keyword(4) | network-on-chip |
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| 1st Author's Name | Hiroki Katano |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | SeungJu Lee |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Takashi Aoki |
| 4th Author's Affiliation | Nippon Telegraph and Telephone Corporation (NTT) |
| 5th Author's Name | Yusuke Sekihara |
| 5th Author's Affiliation | Nippon Telegraph and Telephone Corporation (NTT) |
| 6th Author's Name | Mamoru Nakanishi |
| 6th Author's Affiliation | Nippon Telegraph and Telephone Corporation (NTT) |
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| Speaker | Author-1 |
| Date Time | 2014-01-29 13:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-126, CPSY2013-97, RECONF2013-80 |
| Volume (vol) | vol.113 |
| Number (no) | no.416(VLD), no.417(CPSY), no.418(RECONF) |
| Page | pp.143-148 |
| #Pages | 6 |
| Date of Issue | 2014-01-21 (VLD, CPSY, RECONF) |
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