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Paper Abstract and Keywords
Presentation 2014-01-29 15:15
A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design
Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84
Abstract (in Japanese) (See Japanese page) 
(in English) In order to reduce the power consumption of LSI,
unnecessary parts should be powered off with fine granularity,
and current status data before power-off should be stored for the behavior after power-on.
Next generation non-volatile memory is expected to be used to store data for power-off.
However, the writing power of non-volatile memory is about 10 times higher than that of CMOS memory, so the reduction of writing behaviors
is very important to reduce the total energy.
The manuscript proposes a reduction method of writing behaviors using the difference of the original data and the new data for monitoring data sequences such as wireless sensor nodes.
With the redundancy of the difference and the original data, the number of writing bits for these registers can be saved.
The modificaiton system for the original and differential data registers has been developed and its power consumption has been evaluated.
When applying to temperature monitoring, 24 % writing bits reduction and
11 % power reduction can be obtained.
Keyword (in Japanese) (See Japanese page) 
(in English) Next generation non-volatile memory / Low-power LSI design method / Writing reduction / MTJ based STT-MRAM / EXOR-based clock gating / Fine grain power gating / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 416, VLD2013-130, pp. 167-172, Jan. 2014.
Paper # VLD2013-130 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-130 CPSY2013-101 RECONF2013-84

Conference Information
Committee IPSJ-SLDM CPSY RECONF VLD  
Conference Date 2014-01-28 - 2014-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2014-01-SLDM-CPSY-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design 
Sub Title (in English)  
Keyword(1) Next generation non-volatile memory  
Keyword(2) Low-power LSI design method  
Keyword(3) Writing reduction  
Keyword(4) MTJ based STT-MRAM  
Keyword(5) EXOR-based clock gating  
Keyword(6) Fine grain power gating  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroyuki Shinohara  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Shinji Kimura  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2014-01-29 15:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-130, CPSY2013-101, RECONF2013-84 
Volume (vol) vol.113 
Number (no) no.416(VLD), no.417(CPSY), no.418(RECONF) 
Page pp.167-172 
#Pages 6 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 

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