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| Presentation | 2014-02-10 16:00 A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ)  DC2013-89 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the deep submicron era. Therefore, it is an important problem to reduce capture power dissipation. It was reported that a multi-cycle BIST scheme could reduce capture power dissipation. In this paper, we propose a test generation for broad side scan testing using multi-cycle capture test generation to reduce capture power dissipation by paying our attention to this point. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | transition faults / low power dissipation / multi-cycle capture test generation / untestable faults / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 430, DC2013-89, pp. 61-66, Feb. 2014. | |
| Paper # | DC2013-89 | |
| Date of Issue | 2014-02-03 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2013-89 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2014-02-10 - 2014-02-10 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2014-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation |
| Sub Title (in English) | |
| Keyword(1) | transition faults |
| Keyword(2) | low power dissipation |
| Keyword(3) | multi-cycle capture test generation |
| Keyword(4) | untestable faults |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroshi Yamazaki |
| 1st Author's Affiliation | Nihon University (Nihon Univ) |
| 2nd Author's Name | Yuto Kawatsure |
| 2nd Author's Affiliation | Nihon University (Nihon Univ) |
| 3rd Author's Name | Jun Nishimaki |
| 3rd Author's Affiliation | Nihon University (Nihon Univ) |
| 4th Author's Name | Atsushi Hirai |
| 4th Author's Affiliation | Nihon University (Nihon Univ) |
| 5th Author's Name | Toshinori Hosokawa |
| 5th Author's Affiliation | Nihon University (Nihon Univ) |
| 6th Author's Name | Masayoshi Yoshimura |
| 6th Author's Affiliation | Kyushu University (Kyushu Univ) |
| 7th Author's Name | Koji Yamazaki |
| 7th Author's Affiliation | Meiji University (Meiji Univ) |
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| Speaker | Author-1 |
| Date Time | 2014-02-10 16:00:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2013-89 |
| Volume (vol) | vol.113 |
| Number (no) | no.430 |
| Page | pp.61-66 |
| #Pages | 6 |
| Date of Issue | 2014-02-03 (DC) |
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