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Paper Abstract and Keywords
Presentation 2014-02-10 15:10
A reduction method of shift data volume on BAST
Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ) DC2013-87
Abstract (in Japanese) (See Japanese page) 
(in English) BAST is one of techniques to reduce the amount of test data while maintaining the high test quality using built-in self test and deterministic test generation. On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns. BAST codes, which are test data on BAST, are composed of shift instructions and bit-flipping instructions. The number of shift instructions depends on the number of deterministic patterns and the scan chain length, and the number of bit-flipping instructions depends on the number of conflicts between deterministic patterns and pseudo random patterns. In this paper, we propose a new shift instruction which successively conducts shift operations for specified cycles to reduce the number of shift instructions. Experimental results show that the proposed method was effective to reduce the number of shift instructions for ISCAS'89 and ITC'99 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) BAST architecture / shift instructions / BAST code / bit-flipping instructions / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 430, DC2013-87, pp. 49-54, Feb. 2014.
Paper # DC2013-87 
Date of Issue 2014-02-03 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2014-02-10 - 2014-02-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2014-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A reduction method of shift data volume on BAST 
Sub Title (in English)  
Keyword(1) BAST architecture  
Keyword(2) shift instructions  
Keyword(3) BAST code  
Keyword(4) bit-flipping instructions  
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1st Author's Name Marika Tanaka  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Hiroshi Yamazaki  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon University (Nihon Univ)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyushu University (Kyushu Univ)
5th Author's Name Masayuki Arai  
5th Author's Affiliation Nihon University (Nihon Univ)
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Speaker Author-1 
Date Time 2014-02-10 15:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2013-87 
Volume (vol) vol.113 
Number (no) no.430 
Page pp.49-54 
#Pages 6 
Date of Issue 2014-02-03 (DC) 

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