| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2014-03-03 16:00 Latch-based AES Encryption Circuit Against Fault Analysis Youhua Shi, Hiroaki Taniguchi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)  VLD2013-140 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In general, cryptography is considered to be secure because it is based on complicated mathematical theories. In recent year, however, attacks on not crypto algorithms but hardware implementations such as fault analysis methods have posed new security threats. Cryptographic circuits are prone to fault analysis that intend to retrieve secret data by means of malicious fault injection. Clock-adjustment, voltage change, and laser manipulation can be used to inject malicious faults during the execution of a crypto circuit. As countermeasures against fault analysis, area-redundant methods such as triple modular redundant(TMR) and timing-redundant methods have been proposed at the cost of area or throughput. In this paper, we proposed a latch-based AES encryption circuit, with 18.1% area overhead and 5% throughput improvement, which can detect all the possible errors during the fault analysis region of clock glitch based fault analysis. In addition to fault analysis detection, the proposed method can also prevent the transmission and the use of erroneous results, and then can guarantee the correctness of the final encrypted outputs. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | advanced encryption standard / side-channel attacks / fault analysis / time borrowing end{ekeyword} / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 454, VLD2013-140, pp. 37-42, March 2014. | |
| Paper # | VLD2013-140 | |
| Date of Issue | 2014-02-24 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-140 |
|
| Conference Information | |
| Committee | VLD |
| Conference Date | 2014-03-03 - 2014-03-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Latch-based AES Encryption Circuit Against Fault Analysis |
| Sub Title (in English) | |
| Keyword(1) | advanced encryption standard |
| Keyword(2) | side-channel attacks |
| Keyword(3) | fault analysis |
| Keyword(4) | time borrowing end{ekeyword} |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Youhua Shi |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Hiroaki Taniguchi |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Masao Yanagisawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2014-03-03 16:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-140 |
| Volume (vol) | vol.113 |
| Number (no) | no.454 |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2014-02-24 (VLD) |
[Return to Top Page]