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Paper Abstract and Keywords
Presentation 2014-03-04 14:10
On-wafer de-embedding pattern design for reduced uncertainty under an area constraint
Masafumi Suizu, Akihiko Orii, Kyoya Takano, Mizuki Motoyoshi, Kosuke Katayama, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima (Hiroshima Univ.) MW2013-203
Abstract (in Japanese) (See Japanese page) 
(in English) To obtain the characteristics of the individual devices in the high-frequency measurement, de-embedding is required to remove the influence of the pads from the measurement results. For more accurate extraction of parameters, it is necessary to consider the uncertainty of the on-wafer de-embedding. We propose a method for designing the layout of on-wafer de-embedding patterns for multiline TRL with minimal uncertainty in de-embedding under a chip area constraint.
Keyword (in Japanese) (See Japanese page) 
(in English) On-wafer de-embedding / Uncertainty / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 460, MW2013-203, pp. 35-40, March 2014.
Paper # MW2013-203 
Date of Issue 2014-02-25 (MW) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee MW  
Conference Date 2014-03-04 - 2014-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Ehime University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Microwave Technologies 
Paper Information
Registration To MW 
Conference Code 2014-03-MW 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On-wafer de-embedding pattern design for reduced uncertainty under an area constraint 
Sub Title (in English)  
Keyword(1) On-wafer de-embedding  
Keyword(2) Uncertainty  
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1st Author's Name Masafumi Suizu  
1st Author's Affiliation Hiroshima University (Hiroshima Univ.)
2nd Author's Name Akihiko Orii  
2nd Author's Affiliation Hiroshima University (Hiroshima Univ.)
3rd Author's Name Kyoya Takano  
3rd Author's Affiliation Hiroshima University (Hiroshima Univ.)
4th Author's Name Mizuki Motoyoshi  
4th Author's Affiliation Hiroshima University (Hiroshima Univ.)
5th Author's Name Kosuke Katayama  
5th Author's Affiliation Hiroshima University (Hiroshima Univ.)
6th Author's Name Takeshi Yoshida  
6th Author's Affiliation Hiroshima University (Hiroshima Univ.)
7th Author's Name Shuhei Amakawa  
7th Author's Affiliation Hiroshima University (Hiroshima Univ.)
8th Author's Name Minoru Fujishima  
8th Author's Affiliation Hiroshima University (Hiroshima Univ.)
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Speaker Author-1 
Date Time 2014-03-04 14:10:00 
Presentation Time 25 minutes 
Registration for MW 
Paper # MW2013-203 
Volume (vol) vol.113 
Number (no) no.460 
Page pp.35-40 
#Pages 6 
Date of Issue 2014-02-25 (MW) 

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