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Paper Abstract and Keywords
Presentation 2014-03-04 16:10
[Memorial Lecture] Co-simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki (Mie Univ.), Eric Rotenberg (NCSU), Toshio Kondo (Mie Univ.) VLD2013-154
Abstract (in Japanese) (See Japanese page) 
(in English) As a processor has commonly employed complex microarchitecture, designing a state-of-the-art processor with less effort has become essential for processor research.
In this paper, we propose a co-simulation framework for not only RTL simulation but also gate/transistor level simulation, and even chip evaluation with an LSI tester.
Our framework includes an off-chip system call emulation mechanism that handles system calls using general load and store instructions.
This enables the processor design to involve the execution of general benchmark programs without pseudo-circuits in the processor design.
We also propose a checkpoint mechanism that resumes a program from a pre-created checkpoint.
Moreover, we propose a cache warming mechanism when resuming from a checkpoint.
These mechanisms never require any extra hardware in the processor design and can be consistently used from RTL design to chip fabrication.
Therefore, our co-simulation environment streamlines processor development on standard ASIC flows.
Keyword (in Japanese) (See Japanese page) 
(in English) co-simulation / development environment / ASIC design / microprocessor / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 454, VLD2013-154, pp. 113-113, March 2014.
Paper # VLD2013-154 
Date of Issue 2014-02-24 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD  
Conference Date 2014-03-03 - 2014-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2014-03-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Co-simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow 
Sub Title (in English)  
Keyword(1) co-simulation  
Keyword(2) development environment  
Keyword(3) ASIC design  
Keyword(4) microprocessor  
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1st Author's Name Tomoyuki Nakabayashi  
1st Author's Affiliation Mie University (Mie Univ.)
2nd Author's Name Tomoyuki Sugiyama  
2nd Author's Affiliation Mie University (Mie Univ.)
3rd Author's Name Takahiro Sasaki  
3rd Author's Affiliation Mie University (Mie Univ.)
4th Author's Name Eric Rotenberg  
4th Author's Affiliation North Carolina State University (NCSU)
5th Author's Name Toshio Kondo  
5th Author's Affiliation Mie University (Mie Univ.)
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Speaker Author-1 
Date Time 2014-03-04 16:10:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-154 
Volume (vol) vol.113 
Number (no) no.454 
Page p.113 
#Pages 1 
Date of Issue 2014-02-24 (VLD) 

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