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Paper Abstract and Keywords
Presentation 2014-05-29 13:50
SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier
Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2014-8
Abstract (in Japanese) (See Japanese page) 
(in English) Thanks to recent advances, the size of transistor shrinks and degree of integration becomes high. Butbecause of that advances, synchronous circuit has some problems. One of the problems is PVT variation. This problem increases timing margin and that decreases efficiency of calculation and power consumption. To solve this problem, we propose gate level dual pipeline self synchronous circuit. This circuit uses DCVSL and has precharge phase. In general, precharge phase causes loss of time but this circuit can conceal the overhead of precharge phase by using dual pipeline architecture. In this paper, we introduce Gate Level Dual Pipeline Self-Synchronous Wallace
Tree Multiplier.
Keyword (in Japanese) (See Japanese page) 
(in English) Self Synchronous Circuit / Dual Pipeline / Wallace Tree / Multiplier / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 59, VLD2014-8, pp. 39-44, May 2014.
Paper # VLD2014-8 
Date of Issue 2014-05-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-8

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2014-05-28 - 2014-05-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2014-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier 
Sub Title (in English)  
Keyword(1) Self Synchronous Circuit  
Keyword(2) Dual Pipeline  
Keyword(3) Wallace Tree  
Keyword(4) Multiplier  
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Keyword(6)  
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Keyword(8)  
1st Author's Name Masato Tamura  
1st Author's Affiliation Tokyo University (Univ. of Tokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation Tokyo University (Univ. of Tokyo)
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Speaker Author-1 
Date Time 2014-05-29 13:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2014-8 
Volume (vol) vol.114 
Number (no) no.59 
Page pp.39-44 
#Pages 6 
Date of Issue 2014-05-22 (VLD) 

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