| Paper Abstract and Keywords |
| Presentation |
2014-06-19 11:05
Control of Stacking Fault Structures in Ge1-xSnx Epitaxial Growth Takanori Asano (Nagoya Univ.), Noriyuki Taoka (IHP Microelectronics), Osamu Nakatsuka, Shigeaki Zaima (Nagoya Univ.) SDM2014-47 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Ge or Ge1-xSnx layer with (110) surface has attracted much attentions for Ge multi-gate MOS transistors. For forming a high-quality layer on Ge(110), it is important to suppress the formation of twin or stacking fault (SF). We found that the SF width can be decreased by increasing the Sn content based on understanding the relationship between the defect morphologies and the Sn content. We also found that the defects in Ge1-xSnx with a small Sn content are suppressed by increasing the growth temperature. We demonstrate that defects in Ge and Ge1-xSnx layers can be controlled by the growth temperature and Sn content. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Ge1-xSnx / epitaxial growth / stacking fault / strain / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 114, no. 88, SDM2014-47, pp. 21-25, June 2014. |
| Paper # |
SDM2014-47 |
| Date of Issue |
2014-06-12 (SDM) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
SDM2014-47 |
| Conference Information |
| Committee |
SDM |
| Conference Date |
2014-06-19 - 2014-06-19 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
VBL, Nagoya Univ. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Material Science and Process Technology for MOS Devices and Memories |
| Paper Information |
| Registration To |
SDM |
| Conference Code |
2014-06-SDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Control of Stacking Fault Structures in Ge1-xSnx Epitaxial Growth |
| Sub Title (in English) |
|
| Keyword(1) |
Ge1-xSnx |
| Keyword(2) |
epitaxial growth |
| Keyword(3) |
stacking fault |
| Keyword(4) |
strain |
| Keyword(5) |
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| Keyword(6) |
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| 1st Author's Name |
Takanori Asano |
| 1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
| 2nd Author's Name |
Noriyuki Taoka |
| 2nd Author's Affiliation |
Innovations for High Performance Microelectronics (IHP Microelectronics) |
| 3rd Author's Name |
Osamu Nakatsuka |
| 3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
| 4th Author's Name |
Shigeaki Zaima |
| 4th Author's Affiliation |
Nagoya University (Nagoya Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2014-06-19 11:05:00 |
| Presentation Time |
20 minutes |
| Registration for |
SDM |
| Paper # |
SDM2014-47 |
| Volume (vol) |
vol.114 |
| Number (no) |
no.88 |
| Page |
pp.21-25 |
| #Pages |
5 |
| Date of Issue |
2014-06-12 (SDM) |