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| Presentation | 2014-06-20 10:35 Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Yu-ichi Hayashi, Naofumi Homma (Tohoku Univ.), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech)  EMCJ2014-10 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator chip for the first time. The silicon substrate is essentially common to every circuit and inevitably carries the leakage to the observation taps located at the front as well as at the bottom surface of a die, even if the power and ground wires of an AES module are intentionally separated from the other building blocks. Substrate leakage channels may break the hiding of a cryptographic module regarding its location on a die. The physical properties including the distance dependency are experimentally explored. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Side-channel attack / Power analysis attack / On-chip monitor / substrate noise / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 93, EMCJ2014-10, pp. 1-6, June 2014. | |
| Paper # | EMCJ2014-10 | |
| Date of Issue | 2014-06-13 (EMCJ) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | EMCJ2014-10 |
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| Conference Information | |
| Committee | EMCJ IEE-EMC |
| Conference Date | 2014-06-20 - 2014-06-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kobe Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | PCB, Information Security, EMC |
| Paper Information | |
| Registration To | EMCJ |
| Conference Code | 2014-06-EMCJ-EMC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip |
| Sub Title (in English) | |
| Keyword(1) | Side-channel attack |
| Keyword(2) | Power analysis attack |
| Keyword(3) | On-chip monitor |
| Keyword(4) | substrate noise |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Daisuke Fujimoto |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Noriyuki Miura |
| 2nd Author's Affiliation | Kobe University (Kobe Univ.) |
| 3rd Author's Name | Makoto Nagata |
| 3rd Author's Affiliation | Kobe University (Kobe Univ.) |
| 4th Author's Name | Yu-ichi Hayashi |
| 4th Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 5th Author's Name | Naofumi Homma |
| 5th Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 6th Author's Name | Shivam Bhasin |
| 6th Author's Affiliation | Telecom Paristech (Telecom Paristech) |
| 7th Author's Name | Jean-Luc Danger |
| 7th Author's Affiliation | Telecom Paristech (Telecom Paristech) |
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| Speaker | Author-1 |
| Date Time | 2014-06-20 10:35:00 |
| Presentation Time | 25 minutes |
| Registration for | EMCJ |
| Paper # | EMCJ2014-10 |
| Volume (vol) | vol.114 |
| Number (no) | no.93 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2014-06-13 (EMCJ) |
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