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| Presentation | 2014-06-20 14:30 Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.)  DC2014-13 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay of a circuit under test, and is one of factors of test accuracy degradation. Multi-cycle test is a method that can reduce the voltage drop by repetition of the capture operation. This paper investigates how the reduction of switching activities by the multi-cycle test method reduces the actual voltage drop from observation of power supply voltage of a TEG chip implementing a low-power BIST. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | BIST / scan test / multi-cycle test / capture power / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 99, DC2014-13, pp. 21-26, June 2014. | |
| Paper # | DC2014-13 | |
| Date of Issue | 2014-06-13 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2014-13 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2014-06-20 - 2014-06-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design/Test/Verification |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2014-06-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | scan test |
| Keyword(3) | multi-cycle test |
| Keyword(4) | capture power |
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| 1st Author's Name | Toshiya Nishida |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
| 2nd Author's Name | Senling Wang |
| 2nd Author's Affiliation | Ehime University (Ehime Univ.) |
| 3rd Author's Name | Yasuo Sato |
| 3rd Author's Affiliation | Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
| 4th Author's Name | Seiji Kajihara |
| 4th Author's Affiliation | Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2014-06-20 14:30:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2014-13 |
| Volume (vol) | vol.114 |
| Number (no) | no.99 |
| Page | pp.21-26 |
| #Pages | 6 |
| Date of Issue | 2014-06-13 (DC) |
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