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Paper Abstract and Keywords
Presentation 2014-07-28 13:15
An FPGA-based Graph Processing Accelerator with PyCoRAM
Shinya Takamaeda-Yamazaki, Tadahiro Edamoto, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-10
Abstract (in Japanese) (See Japanese page) 
(in English) In order to improve the programmablity of FPGA-based accelerators with higher performance, we are developing PyCoRAM that abstracts away both on-chip memory (such as BRAM) and off-chip memory (such as DRAM) on an FPGA platform. In this paper, we explore the characteristics of PyCoRAM for complicated applications with irregular memory access patterns. We develop the Dijkstra's algorithm on an FPGA with PyCoRAM, as a typical application consisting irregular memory access patterns. In order to measure the impact of on-chip interconnection systems to execution time, we evaluate the accelerator with several variations of interconnection settings. The evaluation results show that the letency-oriented and narrow shared-bus can achieve about 20% higher performance than the throughput-oriented cross-bar with pipeline registers.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Graph Processing / Dijkstra's Algorithm / PyCoRAM / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 155, CPSY2014-10, pp. 1-6, July 2014.
Paper # CPSY2014-10 
Date of Issue 2014-07-21 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-10

Conference Information
Committee CPSY DC  
Conference Date 2014-07-28 - 2014-07-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Toki Messe, Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2014-07-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA-based Graph Processing Accelerator with PyCoRAM 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Graph Processing  
Keyword(3) Dijkstra's Algorithm  
Keyword(4) PyCoRAM  
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1st Author's Name Shinya Takamaeda-Yamazaki  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Tadahiro Edamoto  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Jun Yao  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2014-07-28 13:15:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-10 
Volume (vol) vol.114 
Number (no) no.155 
Page pp.1-6 
#Pages 6 
Date of Issue 2014-07-21 (CPSY) 

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