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Paper Abstract and Keywords
Presentation 2014-07-28 18:15
Performance Evaluation of Speculative Parallel Processing Utilizing Hardware Transactional Memory on Commercial Multi-core CPU
Yutaka Matsuno, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2014-16
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, it becomes essential to use parallel computation utilizing thread level parallelism as a method to utilize a spreading multi-core processor effectively.
It is considered that speculative parallel processing is effective as a method to further improve its performance.
However, a large overhead occurs to implement speculative parallel processing.
Therefore, measures to that overhead is essential.
In this paper, we considers the method which solves the problem of the overhead by utilizing the hardware transactional memory for recovery process on speculation failure.
We apply a pre-computation method using a helper thread that is one of the speculative parallel processing method to the program of Dijkstra's algorithm that solves the shortest path problem of the graph.
And, we analyze the speculative parallel processing method utilizing hardware transactional memory by evaluating its performance.
Keyword (in Japanese) (See Japanese page) 
(in English) helper thread / dijkstra's algorithm / hardware transactional memory / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 155, CPSY2014-16, pp. 37-42, July 2014.
Paper # CPSY2014-16 
Date of Issue 2014-07-21 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-16

Conference Information
Committee CPSY DC  
Conference Date 2014-07-28 - 2014-07-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Toki Messe, Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2014-07-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation of Speculative Parallel Processing Utilizing Hardware Transactional Memory on Commercial Multi-core CPU 
Sub Title (in English)  
Keyword(1) helper thread  
Keyword(2) dijkstra's algorithm  
Keyword(3) hardware transactional memory  
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1st Author's Name Yutaka Matsuno  
1st Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
2nd Author's Name Kanemitsu Ootsu  
2nd Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
3rd Author's Name Takeshi Ohkawa  
3rd Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
4th Author's Name Takashi Yokota  
4th Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
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Speaker Author-1 
Date Time 2014-07-28 18:15:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-16 
Volume (vol) vol.114 
Number (no) no.155 
Page pp.37-42 
#Pages 6 
Date of Issue 2014-07-21 (CPSY) 

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