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Paper Abstract and Keywords
Presentation 2014-07-29 09:00
Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism
Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HDL. However, there exist two issues to implement a complex algorithm into hardware, which brings growing scale of a synthesized circuit and time for simulation. Therefore, though partitioning a circuit into multiple FPGAs is currently put into practical use, there are two constrains in implementation; the scale and the number of I/O blocks in an FPGA. Thus it is difficult to build a verification environment. In this study, we partition a circuit synthesized by a high-level synthesis tool into some reduced circuits. Moreover, the small circuits are equipped with self-verification function with generating a wrapper for each circuit verification. An FFT circuit which is generated by a high-level synthesis tool is partitioned by our proposed circuit partitioning mechanism. We verify the partitioned circuits in RTL simulation as well as implementation on an FPGA in order to confirm our targeted circuits are correctly operated.
Keyword (in Japanese) (See Japanese page) 
(in English) High Levek Synthesize / HLS / Circuit Partitioning / Circuit Verification / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 155, CPSY2014-17, pp. 43-48, July 2014.
Paper # CPSY2014-17 
Date of Issue 2014-07-21 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY DC  
Conference Date 2014-07-28 - 2014-07-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Toki Messe, Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2014-07-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism 
Sub Title (in English)  
Keyword(1) High Levek Synthesize  
Keyword(2) HLS  
Keyword(3) Circuit Partitioning  
Keyword(4) Circuit Verification  
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1st Author's Name Kazuya Matsuda  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TAT)
2nd Author's Name Takefumi Miyoshi  
2nd Author's Affiliation e-trees.Japan,Inc (e-trees.Japan)
3rd Author's Name Masashi Takemoto  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TAT)
4th Author's Name Satoshi Funada  
4th Author's Affiliation e-trees.Japan,Inc (e-trees.Japan)
5th Author's Name Hironori Nakajo  
5th Author's Affiliation Tokyo University of Agriculture and Technology (TAT)
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Speaker Author-1 
Date Time 2014-07-29 09:00:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-17 
Volume (vol) vol.114 
Number (no) no.155 
Page pp.43-48 
#Pages
Date of Issue 2014-07-21 (CPSY) 


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