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Paper Abstract and Keywords
Presentation 2014-07-29 11:35
Alterable uniform and random NoC through rewiring
Seiichi Tade, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-22
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, the number of cores inside a chip has been increased. Network-on-Chip(NoC) is widely utilized for communication among cores.
The reduction of the communication latency in NoCs has been an essential requirement.
Here, we propose a novel NoC architecture to reduce the communication latency of NoCs.
It configures static random shortcut links when the chip is powered on.
By using random shortcut links, we can exploit the benefit of small world network and reduce the latency. Common regular typologies like torus can be also configured.
Analysis results show that the average graph length of 2D NoC is reduced by 24.5% and 3D NoC by 44.0% at maximum.
The communication latency is drastically reduced for various traffic patterns.
Keyword (in Japanese) (See Japanese page) 
(in English) Network-on-Chip / Small-world network / Random links / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 155, CPSY2014-22, pp. 73-78, July 2014.
Paper # CPSY2014-22 
Date of Issue 2014-07-21 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-22

Conference Information
Committee CPSY DC  
Conference Date 2014-07-28 - 2014-07-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Toki Messe, Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2014-07-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Alterable uniform and random NoC through rewiring 
Sub Title (in English)  
Keyword(1) Network-on-Chip  
Keyword(2) Small-world network  
Keyword(3) Random links  
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1st Author's Name Seiichi Tade  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Ryuta Kawano  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Hiroki Matsutani  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Michihiro Koibuchi  
4th Author's Affiliation National Institute of Informatics (NII)
5th Author's Name Hideharu Amano  
5th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2014-07-29 11:35:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-22 
Volume (vol) vol.114 
Number (no) no.155 
Page pp.73-78 
#Pages 6 
Date of Issue 2014-07-21 (CPSY) 

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