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Paper Abstract and Keywords
Presentation 2014-08-01 14:20
Analysis of Mechanisms of Delay Time Generation in III-V DG MOSFETs
Yuki Yajima, Ryoko Ohama, Sachie Fujikawa, Hiroki I. Fujishiro (TUS) ED2014-57
Abstract (in Japanese) (See Japanese page) 
(in English) III-V semiconductors have attracted much attention as promising n-type channel materials for the future logic device to enter the CMOS roadmap beyond Si, because of their higher carrier mobility and smaller effective mass than Si. In this study, we analysis the delay times in the nanoscale III-V DG MOSFETs by using the quantum-corrected Monte Carlo (QC-MC) simulation. From the results, it is revealed that the delay time distribution is divided into three areas, which are related to the change of the momentum distribution of the electrons, the electron transit time in the channel, the momentum and energy relaxation of the electrons, respectively. We also compare the delay times in the InGaAs, InP, and GaAs channels. The results show the superiority of the InP channel in the switching characteristics.
Keyword (in Japanese) (See Japanese page) 
(in English) InGaAs / GaAs / InP / Double Gate MOSFET / Delay Time / Quantum-Corrected Monte Carlo Method / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 168, ED2014-57, pp. 25-28, Aug. 2014.
Paper # ED2014-57 
Date of Issue 2014-07-25 (ED) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2014-57

Conference Information
Committee ED  
Conference Date 2014-08-01 - 2014-08-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. B3-1 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Semiconductor Process and Devices (surface, interface, reliability), others 
Paper Information
Registration To ED 
Conference Code 2014-07-ED 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Mechanisms of Delay Time Generation in III-V DG MOSFETs 
Sub Title (in English)  
Keyword(1) InGaAs  
Keyword(2) GaAs  
Keyword(3) InP  
Keyword(4) Double Gate MOSFET  
Keyword(5) Delay Time  
Keyword(6) Quantum-Corrected Monte Carlo Method  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuki Yajima  
1st Author's Affiliation Tokyo University of Science (TUS)
2nd Author's Name Ryoko Ohama  
2nd Author's Affiliation Tokyo University of Science (TUS)
3rd Author's Name Sachie Fujikawa  
3rd Author's Affiliation Tokyo University of Science (TUS)
4th Author's Name Hiroki I. Fujishiro  
4th Author's Affiliation Tokyo University of Science (TUS)
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Speaker Author-1 
Date Time 2014-08-01 14:20:00 
Presentation Time 25 minutes 
Registration for ED 
Paper # ED2014-57 
Volume (vol) vol.114 
Number (no) no.168 
Page pp.25-28 
#Pages 4 
Date of Issue 2014-07-25 (ED) 

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