| 電子情報通信学会 研究会発表申込システム 講演論文 詳細 |
技報閲覧サービス [ログイン] 技報アーカイブ |
| トップに戻る | 前のページに戻る | [Japanese] / [English] |
| 講演抄録／キーワード | ||
| 講演名 | 2014-10-24 11:40 The Design and Development of Synthetic Aperture Radar (SAR) Imaging Field Programmable Gate Array (FPGA)-based Processor ○Yung Chong Lee・Voon Chet Koo・Yee Kit Chan（Multimedia Univ.）  SANE2014-100 |
|
| 抄録 | （和） | Synthetic Aperture Radar (SAR) is an all-weather microwave remote sensing system which is invented from the concept of creating and synthesizing a very much longer antenna aperture size with a smaller antenna aperture size by using signal processing techniques to produce a high resolution image of the measured earth?s surface. Range-Doppler algorithm (RDA) is the first discovered digital processing algorithm used for the processing of SAR data and it is able to achieve block processing efficiency by using frequency domain operations in both range and azimuth directions at the same time maintaining the 1-Dimensional operation simplicity. Fast Fourier Transform (FFT) is the prerequisite in the RDA as it is used to transform the SAR data into frequency domain for match filtering operations. RDA become formidable and arduous without the use of FFT and IFFT as the majority of computation time and processing power (about 70%) in RDA are occupied by FFTs and IFFTs. Field-Programmable Gate Array (FPGA)-based SAR processing system approaches to the fast demand process of SAR data due to the hardware implementation of FPGA-based system exploit flexibility, reconfigurability, pipelining and massively parallel processing which yield in faster and cost-effective designs. On board storage of SAR data usually not feasible due to quick response demands, power consumption and space limitations of the carrier system. Thus, on-board processing capability is one of the most desired and demanded abilities in the SAR processing system. This article highlights the design and development of an FPGA-based SAR processor. An efficient reconfigurable FFT core and IFFT core have been designed and developed by using hardware description language (HDL). From the simulation results, the proposed architectures significantly reduced the usage of hardware resources in an FPGA while achieving the reasonably high processing speed and throughput rate with the reconfigurable ability. |
| （英） | Synthetic Aperture Radar (SAR) is an all-weather microwave remote sensing system which is invented from the concept of creating and synthesizing a very much longer antenna aperture size with a smaller antenna aperture size by using signal processing techniques to produce a high resolution image of the measured earth?s surface. Range-Doppler algorithm (RDA) is the first discovered digital processing algorithm used for the processing of SAR data and it is able to achieve block processing efficiency by using frequency domain operations in both range and azimuth directions at the same time maintaining the 1-Dimensional operation simplicity. Fast Fourier Transform (FFT) is the prerequisite in the RDA as it is used to transform the SAR data into frequency domain for match filtering operations. RDA become formidable and arduous without the use of FFT and IFFT as the majority of computation time and processing power (about 70%) in RDA are occupied by FFTs and IFFTs. Field-Programmable Gate Array (FPGA)-based SAR processing system approaches to the fast demand process of SAR data due to the hardware implementation of FPGA-based system exploit flexibility, reconfigurability, pipelining and massively parallel processing which yield in faster and cost-effective designs. On board storage of SAR data usually not feasible due to quick response demands, power consumption and space limitations of the carrier system. Thus, on-board processing capability is one of the most desired and demanded abilities in the SAR processing system. This article highlights the design and development of an FPGA-based SAR processor. An efficient reconfigurable FFT core and IFFT core have been designed and developed by using hardware description language (HDL). From the simulation results, the proposed architectures significantly reduced the usage of hardware resources in an FPGA while achieving the reasonably high processing speed and throughput rate with the reconfigurable ability. | |
| キーワード | （和） | Synthetic Aperture Radar / Field Programmable Gate Array / Range-Doppler algorithm / Fast Fourier Transform / Inverse Fast Fourier Transform / Reconfigurability / Pipelining / Matched Filtering |
| （英） | Synthetic Aperture Radar / Field Programmable Gate Array / Range-Doppler algorithm / Fast Fourier Transform / Inverse Fast Fourier Transform / Reconfigurability / Pipelining / Matched Filtering | |
| 文献情報 | 信学技報, vol. 114, no. 264, SANE2014-100, pp. 201-206, 2014年10月. | |
| 資料番号 | SANE2014-100 | |
| 発行日 | 2014-10-15 (SANE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| 著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します．(許諾番号：10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| PDFダウンロード | SANE2014-100 |
|
| 研究会情報 | |
| 研究会 | SANE |
| 開催期間 | 2014-10-22 - 2014-10-24 |
| 開催地（和） | Ramada Plaza Melaka, Malacca, Malaysia |
| 開催地（英） | Ramada Plaza Melaka, Malacca, Malaysia |
| テーマ（和） | ICSANE 2014 (International Conference on Space, Aeronautical and Navigational Electronics) |
| テーマ（英） | ICSANE 2014 (International Conference on Space, Aeronautical and Navigational Electronics) |
| 講演論文情報の詳細 | |
| 申込み研究会 | SANE |
| 会議コード | 2014-10-SANE |
| 本文の言語 | 英語 |
| タイトル（和） | |
| サブタイトル（和） | |
| タイトル（英） | The Design and Development of Synthetic Aperture Radar (SAR) Imaging Field Programmable Gate Array (FPGA)-based Processor |
| サブタイトル（英） | |
| キーワード(1)（和/英） | Synthetic Aperture Radar / Synthetic Aperture Radar |
| キーワード(2)（和/英） | Field Programmable Gate Array / Field Programmable Gate Array |
| キーワード(3)（和/英） | Range-Doppler algorithm / Range-Doppler algorithm |
| キーワード(4)（和/英） | Fast Fourier Transform / Fast Fourier Transform |
| キーワード(5)（和/英） | Inverse Fast Fourier Transform / Inverse Fast Fourier Transform |
| キーワード(6)（和/英） | Reconfigurability / Reconfigurability |
| キーワード(7)（和/英） | Pipelining / Pipelining |
| キーワード(8)（和/英） | Matched Filtering / Matched Filtering |
| 第1著者 氏名（和/英/ヨミ） | Yung Chong Lee / Yung Chong Lee / |
| 第1著者 所属（和/英） | Multimedia Univeristy (略称： Multimedia Univ.) Multimedia Univeristy (略称： Multimedia Univ.) |
| 第2著者 氏名（和/英/ヨミ） | Voon Chet Koo / Voon Chet Koo / |
| 第2著者 所属（和/英） | Multimedia Univeristy (略称： Multimedia Univ.) Multimedia Univeristy (略称： Multimedia Univ.) |
| 第3著者 氏名（和/英/ヨミ） | Yee Kit Chan / Yee Kit Chan / |
| 第3著者 所属（和/英） | Multimedia Univeristy (略称： Multimedia Univ.) Multimedia Univeristy (略称： Multimedia Univ.) |
| 講演者 | 第1著者 |
| 発表日時 | 2014-10-24 11:40:00 |
| 発表時間 | 20分 |
| 申込先研究会 | SANE |
| 資料番号 | SANE2014-100 |
| 巻番号（vol） | vol.114 |
| 号番号（no） | no.264 |
| ページ範囲 | pp.201-206 |
| ページ数 | 6 |
| 発行日 | 2014-10-15 (SANE) |
[研究会発表申込システムのトップページに戻る]