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Paper Abstract and Keywords
Presentation 2014-10-24 11:40
The Design and Development of Synthetic Aperture Radar (SAR) Imaging Field Programmable Gate Array (FPGA)-based Processor
Yung Chong Lee, Voon Chet Koo, Yee Kit Chan (Multimedia Univ.) SANE2014-100
Abstract (in Japanese) (See Japanese page) 
(in English) Synthetic Aperture Radar (SAR) is an all-weather microwave remote sensing system which is invented from the concept of creating and synthesizing a very much longer antenna aperture size with a smaller antenna aperture size by using signal processing techniques to produce a high resolution image of the measured earth?s surface. Range-Doppler algorithm (RDA) is the first discovered digital processing algorithm used for the processing of SAR data and it is able to achieve block processing efficiency by using frequency domain operations in both range and azimuth directions at the same time maintaining the 1-Dimensional operation simplicity. Fast Fourier Transform (FFT) is the prerequisite in the RDA as it is used to transform the SAR data into frequency domain for match filtering operations. RDA become formidable and arduous without the use of FFT and IFFT as the majority of computation time and processing power (about 70%) in RDA are occupied by FFTs and IFFTs. Field-Programmable Gate Array (FPGA)-based SAR processing system approaches to the fast demand process of SAR data due to the hardware implementation of FPGA-based system exploit flexibility, reconfigurability, pipelining and massively parallel processing which yield in faster and cost-effective designs. On board storage of SAR data usually not feasible due to quick response demands, power consumption and space limitations of the carrier system. Thus, on-board processing capability is one of the most desired and demanded abilities in the SAR processing system. This article highlights the design and development of an FPGA-based SAR processor. An efficient reconfigurable FFT core and IFFT core have been designed and developed by using hardware description language (HDL). From the simulation results, the proposed architectures significantly reduced the usage of hardware resources in an FPGA while achieving the reasonably high processing speed and throughput rate with the reconfigurable ability.
Keyword (in Japanese) (See Japanese page) 
(in English) Synthetic Aperture Radar / Field Programmable Gate Array / Range-Doppler algorithm / Fast Fourier Transform / Inverse Fast Fourier Transform / Reconfigurability / Pipelining / Matched Filtering  
Reference Info. IEICE Tech. Rep., vol. 114, no. 264, SANE2014-100, pp. 201-206, Oct. 2014.
Paper # SANE2014-100 
Date of Issue 2014-10-15 (SANE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SANE2014-100

Conference Information
Committee SANE  
Conference Date 2014-10-22 - 2014-10-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Ramada Plaza Melaka, Malacca, Malaysia 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ICSANE 2014 (International Conference on Space, Aeronautical and Navigational Electronics) 
Paper Information
Registration To SANE 
Conference Code 2014-10-SANE 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) The Design and Development of Synthetic Aperture Radar (SAR) Imaging Field Programmable Gate Array (FPGA)-based Processor 
Sub Title (in English)  
Keyword(1) Synthetic Aperture Radar  
Keyword(2) Field Programmable Gate Array  
Keyword(3) Range-Doppler algorithm  
Keyword(4) Fast Fourier Transform  
Keyword(5) Inverse Fast Fourier Transform  
Keyword(6) Reconfigurability  
Keyword(7) Pipelining  
Keyword(8) Matched Filtering  
1st Author's Name Yung Chong Lee  
1st Author's Affiliation Multimedia Univeristy (Multimedia Univ.)
2nd Author's Name Voon Chet Koo  
2nd Author's Affiliation Multimedia Univeristy (Multimedia Univ.)
3rd Author's Name Yee Kit Chan  
3rd Author's Affiliation Multimedia Univeristy (Multimedia Univ.)
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Speaker Author-1 
Date Time 2014-10-24 11:40:00 
Presentation Time 20 minutes 
Registration for SANE 
Paper # SANE2014-100 
Volume (vol) vol.114 
Number (no) no.264 
Page pp.201-206 
#Pages 6 
Date of Issue 2014-10-15 (SANE) 

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