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Paper Abstract and Keywords
Presentation 2014-11-26 09:15
Design of Flip-Flop with Timing Error Tolerance
Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33
Abstract (in Japanese) (See Japanese page) 
(in English) Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the circuit becomes bigger, and margins of the supply voltage and the clock frequency necessary for a design increase. For the mitigation of the margin, the structure of the circuit with the timing error tolerance is studied flourishingly.
In this paper, we propose two new Time Borrowing Flip-Flops (TBFF) in transistor level to realize timing error tolerance by switching from flip-flop to latch dynamically. HSPICE simulation results show that the proposed TBFF can achieve up to 28.1% power reduction when compared with existing works.
Keyword (in Japanese) (See Japanese page) 
(in English) flip-flop / PVT variation / safety margin / time-borrowing / timing error / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-79, pp. 45-50, Nov. 2014.
Paper # VLD2014-79 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-79 DC2014-33

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Flip-Flop with Timing Error Tolerance 
Sub Title (in English)  
Keyword(1) flip-flop  
Keyword(2) PVT variation  
Keyword(3) safety margin  
Keyword(4) time-borrowing  
Keyword(5) timing error  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Taito Suzuki  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Youhua Shi  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Kimiyoshi Usami  
4th Author's Affiliation Shibaura Institute of Technology (SIT)
5th Author's Name Masao Yanagisawa  
5th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2014-11-26 09:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2014-79, DC2014-33 
Volume (vol) vol.114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.45-50 
#Pages 6 
Date of Issue 2014-11-19 (VLD, DC) 

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