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Paper Abstract and Keywords
Presentation 2014-11-26 16:40
An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System
Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima Univ.) VLD2014-76 DC2014-30
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a hardware-oriented speed traffic-sign recognition algorithm and its FPGA architecture in which real-time processing is possible for Advanced Driving Assistant System (ADAS). The proposed algorithm performs the sign detection using binary images, which are converted from a grayscale input images. The proposed method enables real-time speed sign recognition for FPGA implementation by using run lengths of pixel within a candidate region and black and white pixel-histograms in the region which are easily calculated by simple arithmetic and logical operations. From the experimental results, the proposed method achieves the recognition accuracy up to more than a 99 % in daytimes and up to a 94.2 % at nights including rainy night situations.
Keyword (in Japanese) (See Japanese page) 
(in English) Advanced Driver Assistance System (ADAS) / Real-Time Processing / Traffic-Sign Recognition / Number Recognition / FPGA Implementation / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-76, pp. 27-32, Nov. 2014.
Paper # VLD2014-76 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-76 DC2014-30

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System 
Sub Title (in English)  
Keyword(1) Advanced Driver Assistance System (ADAS)  
Keyword(2) Real-Time Processing  
Keyword(3) Traffic-Sign Recognition  
Keyword(4) Number Recognition  
Keyword(5) FPGA Implementation  
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Keyword(7)  
Keyword(8)  
1st Author's Name Masaharu Yamamoto  
1st Author's Affiliation Hiroshima University (Hiroshima Univ.)
2nd Author's Name Anh-Tuan Hoang  
2nd Author's Affiliation Hiroshima University (Hiroshima Univ.)
3rd Author's Name Tetsushi Koide  
3rd Author's Affiliation Hiroshima University (Hiroshima Univ.)
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Speaker Author-1 
Date Time 2014-11-26 16:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2014-76, DC2014-30 
Volume (vol) vol.114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.27-32 
#Pages 6 
Date of Issue 2014-11-19 (VLD, DC) 

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