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Paper Abstract and Keywords
Presentation 2014-12-01 15:15
[Poster Presentation] A Study on a Comprehensive Architecture Exploration Environment for Emerging Applications
Shohei Takeuchi, Shinya Takamaeda Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) ICD2014-77 CPSY2014-89
Abstract (in Japanese) (See Japanese page) 
(in English) Emerging applications, such as graph processing and machine learning, contain several irregular memory access patterns and control flows.
While heterogeneous computing systems which consist of general CPUs and accelerators, such as GPU, have been widely used, the performance contribution given by each microarchitectual component of such hardware is still inapparent.
In this paper, we propose a comprehensive processor evaluation environment that can evaluate various architecture settings.
We evaluate the performance of triangle counting to identify the appropriate instruction window size for a single OoO core.
Keyword (in Japanese) (See Japanese page) 
(in English) Graph processing / Architecture Exploration / Instruction-level parallelism / Thread-level parallelism / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 346, CPSY2014-89, pp. 25-27, Dec. 2014.
Paper # CPSY2014-89 
Date of Issue 2014-11-24 (ICD, CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2014-77 CPSY2014-89

Conference Information
Committee ICD CPSY  
Conference Date 2014-12-01 - 2014-12-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2014-12-ICD-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study on a Comprehensive Architecture Exploration Environment for Emerging Applications 
Sub Title (in English)  
Keyword(1) Graph processing  
Keyword(2) Architecture Exploration  
Keyword(3) Instruction-level parallelism  
Keyword(4) Thread-level parallelism  
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1st Author's Name Shohei Takeuchi  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Shinya Takamaeda Yamazaki  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Jun Yao  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2014-12-01 15:15:00 
Presentation Time 120 minutes 
Registration for CPSY 
Paper # ICD2014-77, CPSY2014-89 
Volume (vol) vol.114 
Number (no) no.345(ICD), no.346(CPSY) 
Page pp.25-27 
#Pages 3 
Date of Issue 2014-11-24 (ICD, CPSY) 

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