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| Presentation | 2014-12-11 15:05 A study on PLL design for high recording density tape system Atsushi Musha (FUJIFILM/Ehime Univ.), Osamu Shimizu (FUJIFILM), Yasuaki Nakamura, Yoshihiro Okamoto (Ehime Univ.)  MR2014-32 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Timing recovery method for high density tape storage system is studied. Since tape system suffers from large speed variation compared to the disk system, the design of a stable PLL circuit which can operate under low signal to noise ratio (SNR) condition is an important issue. In such low SNR circumstance, the decision error made by the detector sometimes leads PLL circuit to lose its track on the correct signal, which is often called the cycle-slip phenomenon. In order to mitigate cycle-slip issue, soft information from the Viterbi detector is utilized. It is clarified that the negative effect of un-reliable decision from the detector can be compensated by controlling the feedback gain of the timing recovery loop dynamically as a function of decision reliability. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Timing recovery / Tape storage system / Viterbi detector / Cycle-slip / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, Dec. 2014. | |
| Paper # | ||
| Date of Issue | 2014-12-04 (MR) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | MR2014-32 |
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| Conference Information | |
| Committee | MRIS ITE-MMS |
| Conference Date | 2014-12-11 - 2014-12-12 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Signal Processing, etc. |
| Paper Information | |
| Registration To | MRIS |
| Conference Code | 2014-12-MR-MMS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study on PLL design for high recording density tape system |
| Sub Title (in English) | |
| Keyword(1) | Timing recovery |
| Keyword(2) | Tape storage system |
| Keyword(3) | Viterbi detector |
| Keyword(4) | Cycle-slip |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Atsushi Musha |
| 1st Author's Affiliation | FUJIFILM Corporation/Ehime University (FUJIFILM/Ehime Univ.) |
| 2nd Author's Name | Osamu Shimizu |
| 2nd Author's Affiliation | FUJIFILM Corporation (FUJIFILM) |
| 3rd Author's Name | Yasuaki Nakamura |
| 3rd Author's Affiliation | Ehime University (Ehime Univ.) |
| 4th Author's Name | Yoshihiro Okamoto |
| 4th Author's Affiliation | Ehime University (Ehime Univ.) |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2014-12-11 15:05:00 |
| Presentation Time | 25 minutes |
| Registration for | MRIS |
| Paper # | MR2014-32 |
| Volume (vol) | vol.114 |
| Number (no) | no.355 |
| Page | pp.23-27 |
| #Pages | 5 |
| Date of Issue | 2014-12-04 (MR) |
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