Paper Abstract and Keywords |
Presentation |
2015-01-27 14:50
[Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 Link to ES Tech. Rep. Archives: SDM2014-142 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, leakage current and large cell size of SRAM is known to be issues. To reduce power and area simultaneously, magnetic tunneling junction (MTJ) based cache memory is considered promising. There are two issues for realizing MTJ based cache memory, one is large write current of MTJ and the other is integration with logic CMOS. In this paper, we develop three technologies to resolve these issues, low power advanced-MTJ development, low temperature integration technology and asymmetric compensation technology which utilize asymmetry of cache data. By proposed technology, cache power can be reduced 60% with only 7% performance overhead. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MTJ / MRAM / STT-MRAM / cache memory / normally-off computing / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 421, SDM2014-142, pp. 29-32, Jan. 2015. |
Paper # |
SDM2014-142 |
Date of Issue |
2015-01-20 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2014-142 Link to ES Tech. Rep. Archives: SDM2014-142 |
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