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Paper Abstract and Keywords
Presentation 2015-01-30 11:50
An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer
Li Ning, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) VLD2014-140 CPSY2014-149 RECONF2014-73
Abstract (in Japanese) (See Japanese page) 
(in English) Due to its effectiveness, machine learning based on deep neural network is getting more and more popular in image and speech recognition area, recently. However, it consumes a large amount of time for training and structure optimization even by high performance computers. In this report, we present a deep convolutional neural network hardware based on 2D single instruction multiple data (SIMD) array and synchronous shift data transfer which is suitable for parallel computing for training and prediction.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Synchronous Shift Data Transfer / Machine Learning / Neural Network / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 426, VLD2014-140, pp. 175-180, Jan. 2015.
Paper # VLD2014-140 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-140 CPSY2014-149 RECONF2014-73

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Synchronous Shift Data Transfer  
Keyword(3) Machine Learning  
Keyword(4) Neural Network  
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1st Author's Name Li Ning  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Yoichi Tomioka  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Hitoshi Kitazawa  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2015-01-30 11:50:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2014-140, CPSY2014-149, RECONF2014-73 
Volume (vol) vol.114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.175-180 
#Pages 6 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 

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