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Paper Abstract and Keywords
Presentation 2015-02-13 15:20
A Method of LFSR Seed Generation for Hierarchical BIST
Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85
Abstract (in Japanese) (See Japanese page) 
(in English) A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST).
In BIST, although pseudo-random patterns generated by the LFSR are applied to a circuit under test (CUT) as test patterns, reseeding, which replaces the seed of the LFSR, is used to detect random pattern resistant faults (RPRFs).
In general, a seed that when expanded by the LFSR will produce a test pattern for an RPRF is used for reseeding.
So far, we have proposed a one-pass seed generation method for generating such a seed for scan based BIST.
In this paper, we employ the concept of the one-pass seed generation for hierarchical BIST methods utilizing register-transfer level (RTL) information.
The proposed method can identify untestable faults under the BIST environment and guarantees to generate seeds for detectable faults.
In our experiments for several RTL benchmark circuits, we show that fault coverage can be improved by using the generated seeds for RPRFs of the circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) BIST / LFSR / seed generation / time expansion model / delay faults / hierarchical BIST / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 446, DC2014-85, pp. 43-48, Feb. 2015.
Paper # DC2014-85 
Date of Issue 2015-02-06 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2015-02-13 - 2015-02-13 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc 
Paper Information
Registration To DC 
Conference Code 2015-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Method of LFSR Seed Generation for Hierarchical BIST 
Sub Title (in English)  
Keyword(1) BIST  
Keyword(2) LFSR  
Keyword(3) seed generation  
Keyword(4) time expansion model  
Keyword(5) delay faults  
Keyword(6) hierarchical BIST  
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Keyword(8)  
1st Author's Name Kosuke Sawaki  
1st Author's Affiliation Oita University (Oita Univ.)
2nd Author's Name Satoshi Ohtake  
2nd Author's Affiliation Oita University (Oita Univ.)
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Speaker Author-1 
Date Time 2015-02-13 15:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2014-85 
Volume (vol) vol.114 
Number (no) no.446 
Page pp.43-48 
#Pages 6 
Date of Issue 2015-02-06 (DC) 

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